Data Sheet

ISM14585-L35 Specification
DOC-DS-14585-201807-3.0
Confidential Inventek Systems
Page 56
• UART_STER_REG accesses the FCR[5-4] register without accessing the other
UART_FCR_REG bits.
9.8.7 DIRECT TEST MODE
The on-chip UARTS can be used for the Direct Test Mode required for the final product
PHY layer testing. It can be done either over the HCI layer, which engages a full
CTS/RTS UART or using a 2- wire UART directly as described in the Bluetooth Low
Energy Specification (Volume 6, Part F).
9.9 SPI+ Interface
This interface supports a subset of the Serial Peripheral Interface (SPI™). The serial
interface can transmit and receive 8, 16 or 32 bits in master/slave mode and transmit 9
bits in master mode. The SPI+ interface has enhanced functionality with bidirectional
2x16-bit word FIFOs.
Features
• Slave and Master mode
• 8 bit, 9 bit, 16 bit or 32 bit operation
• Clock speeds up to 16 MHz for the SPI controller. Programmable output
frequencies of SPI source clock divided by 1, 2, 4, 8
• SPI clock line speed up to 8 MHz
• SPI mode 0, 1, 2, 3 support (clock edge and phase)
• Programmable SPI_DO idle level
• Maskable Interrupt generation
• Bus load reduction by unidirectional writes-only and reads-only modes.
• Built-in RX/TX FIFOs for continuous SPI bursts.
• DMA support