Data Sheet

ISM14585-L35 Specification
DOC-DS-14585-201807-3.0
Confidential Inventek Systems
Page 57
Figure 26 SPI Block Diagram
9.9.1 OPERATION WITHOUT FIFOS
This mode is the default mode.
Master Mode
To enable SPITM operation, first the individual port signal must be enabled. Next the
SPI must be configured in SPI_CTRL_REG, for the desired mode. Finally bit SPI_ON
must be set to 1.
A SPI transfer cycle starts after writing to the SPI_RX_TX_REG0. In case of 32 bits
mode, the PI_RX_TX_REG1 must be written first. Writing to SPI_RX_TX_REG0 also
sets the SPI_TXH. As soon as the holding register is copied to the IO buffer, the
SPI_TXH is reset and a serial transfer cycle of 8/9/16/32 clock-cycles is started which
causes 8/9/16/32 bits to be transmitted on SPI_DO. Simultaneously, data is received on
SPI_DI and shifted into the IO buffer. The transfer cycle finishes after the
8th/9th/16th/32nd clock cycle and SPI_INT_BIT bit is set in the SPI_CTRL_REG and