Data Sheet

ISM14585-L35 Specification
DOC-DS-14585-201807-3.0
Confidential Inventek Systems
Page 58
SPI_INT_PEND bit in (RE)SET_INT_PENDING_REG is set. The received bits in the IO
buffer are copied to the SPI_RX_TX_REG0 (and SPI_RX_TX_REG1 in case of 32 bits
mode) were they can be
read by the CPU.
Interrupts to the CPU can be disabled using the SPI_MINT bit. To clear the SPI interrupt
source, any value to SPI_CLEAR_INT_REG must be written. Note however that
SPI_INT will be set as long as the RX-FIFO contains unread data.
Slave Mode
The slave mode is selected with SPI_SMn set to 1 and the Px_MODE_REG must also
select SPI_CLK as input. The functionality of the IO buffer in slave and master mode is
identical. The SPI module clocks data in on SPI_DI and out on SPI_DO on every active
edge of SPI_CLK. As shown in Figure 24 to Figure 27, Figure 27: SPI Master/slave,
Mode 3: SPI_POL=1 and SPI_PHA=1. The SPI has an active low clock enable SPI_EN,
which can be enabled with bit SPI_EN_CTRL=1.
In slave mode the internal SPI clock must be more than four times the SPI_CLK
In slave mode the SPI_EN serves as a clock enable and bit synchronization If enabled
with bit SPI_EN_CTRL. As soon as SPI_EN is deactivated between the MSB and LSB
bits, the I/O buffer is reset.
SPI_POL and SPI_PHA
The phase and polarity of the serial clock can be changed with bits SPI_POL and
SPI_PHA in the SPI_CTRL_REG.
SPI_DO Idle Levels
The idle level of signal SPI_DO depends on the master or slave mode and polarity and
phase mode of the clock.
In master mode pin SPI_DO gets the value of bit SPI_DO if the SPI is idle in all modes.
Also, if slave in SPI modes 0 and 2, SPI_DO is the initial and final idle level.
In SPI modes 1 and 3 however there is no clock edge after the sampled lsb and pin
SPI_DO gets the lsb value of the IO buffer. If required, the SPI_DO can be forced to the
SPI_DO bit level by resetting the SPI to the idle state by shortly setting bit SPI_RST to
1. (Optionally SPI_FORCE_DO can be set, but this does not reset the IO buffer). The
following diagrams show the timing of the SPITM interface.