Data Sheet

ISM14585-L35 Specification
DOC-DS-14585-201807-3.0
Confidential Inventek Systems
Page 59
Writes Only Mode
In “writes only” mode (SPI_FIFO_MODE = “10“) only the TX-FIFO is used. Received
data will be copied to the SPI_RX_TX_REGx, but if a new SPI transfer is finished before
the old data is read from the memory, this register will be overwritten.
SPI_INT acts as a tx_request signal, indicating that there is still place in the FIFO. It will
be ‘0’ when the FIFO is full or else ‘1’ when it’s not full. This is also indicated in the
SPI_CTRL_REG[SPI_TXH], which is ‘1’ if the TX-FIFO is full. Writing to the FIFO if this
bit is still 1, will result in transmission of undefined data. If all data has been transferred,
SPI_CTRL_REG1 [SPI_BUSY] will become ‘0’.
Reads Only Mode
In “reads only” mode (SPI_FIFO_MODE = “01“) only the RX-FIFO is used. Transfers will
start immediately when the SPI is turned on in this mode. In transmit direction the
SPI_DO pin will transmit the IO buffer contents being the actual value of the
SPI_TX_REGx (all 0’s after reset). This means that no dummy writes are needed for
reads only transfers.
In Slave mode transfers only take place if the external master initiates them, but in
master mode this means that transfers will continue until the RX-FIFO is full. If this
happens SPI_CTRL_REG1[SPI_BUSY] will become ‘0’. If exactly N words need to be
read from SPI device, first read (N - fifosize+1) words. Then wait until the SPI_BUSY
becomes ‘0’, set SPI_FIFO_MODE to “00” and finally read the remaining (fifosize +1)
words. Here fifosize is 4/2/1 words for 8/16/32 bits mode respectively.
If this is not done, more data will be read from the SPI device until the FIFO is
completely filled, or the SPI is turned off.
Bidirectional transfers with FIFO
If SPI_FIFO_MODE is “00“, both registers are used as a FIFO. SPI_TXH indicates that
TX-FIFO is full, SPI_INT indicates that there is data in the RX-FIFO.