Data Sheet

ISM14585-L35 Specification
DOC-DS-14585-201807-3.0
Confidential Inventek Systems
Page 60
Figure 27 SPI Master/Slave, Mode 0: SPI_POL=0 and SPI_PHA=0
Note 1: If 9 bits SPI mode, the MSB bit in transmit direction is determined by bit
SPI_CTRL_REG[SPI_9BIT_VAL]. In receive direction, the MSB is received but not
stored.
Figure 28 SPI Master/Slave, Mode 1: SPI_POL=0 and SPI_PHA=1
For the MSB bit refer to Note 1