Data Sheet

ISM14585-L35 Specification
DOC-DS-14585-201807-3.0
Confidential Inventek Systems
Page 65
Figure 33 Timer 0 Block Diagram
Figure 33 shows the block diagram of Timer 0. The 16 bits timer consists of two
counters: T0-counter and ON-counter, and three registers: TIMER0_RELOAD_M_REG,
TIMER0_RELOAD_N_REG and TIMER0_ON_REG. Upon reset, the counter and
register values are 0x0000. Timer 0 will generate a Pulse Width Modulated signal
PWM0. The frequency and duty cycle of PWM0 are determined by the contents of the
TIMER0_RELOAD_N_REG and the TIMER0_RELOAD_M_REG registers.
The timer can run at five different clocks: 16 MHz, 8 MHz, 4 MHz, 2 MHz or 32 kHz. The
32 kHz clock is selected by default with bit TIM0_CLK_SEL in the TIMER0_CTRL_REG
register. This ‘slow’ clock has no enabling bit. The other four options can be selected by
setting the TIM0_CLK_SEL bit and the TMR_ENABLE bit in the CLK_PER_REG
(default disabled). This register also controls the frequency via the TMR_DIV bits. An
extra clock divider is available that can be activated via bit TIM0_CLK_DIV of the timer
control register TIMER0_CTRL_REG. This clock divider is only used for the ON-counter
and always divides by 10. Timer 0 operates in PWM mode. The signals PWM0 and
PWM1 can be mapped to any GPIOs.