Data Sheet

ISM14585-L35 Specification
DOC-DS-14585-201807-3.0
Confidential Inventek Systems
Page 67
Figure 34 Timer 0 PWM Mode
At start-up both counters and the PWM0 signal are LOW so also at start-up an interrupt
is generated. If Timer 0 is disabled all flip-flops, counters and outputs are in reset state
except for the ON-register, the TIMER0_RELOAD_N_REG register and the
TIMER0_RELOAD_M_REG register.
The timer input registers ON-register, TIMER0_RELOAD_N_REGand
TIMER0_RELOAD_M_REG can be written, and the counter registers ON-counter and
T0-counter can be read. When reading from the address of the ON-register, the value of
the ON-counter is returned. Reading from the address of either the
TIMER0_RELOAD_N_REG or the TIMER0_RELOAD_M_REG register, returns the
value of the T0-counter.
It is possible to freeze Timer 0 with bit FRZ_SWTIM of the register SET_FREEZE_REG.
When the timer is frozen the timer counters are not decremented. This will freeze all the
timer registers at their last value. The timer will continue its operation again when bit
FRZ_SWTIM is cleared via register RESET_FREEZE_REG.
9.11.2 TIMER 2
Timer 2 has three Pulse Width Modulated (PWM) outputs. The block diagram is shown
in Figure 35
Features:
• 14-bit general purpose timer
• Ability to generate 3 Pulse Width Modulated signals (PWM2, PWM3 and PWM4)