Data Sheet

ISM14585-L35 Specification
DOC-DS-14585-201807-3.0
Confidential Inventek Systems
Page 69
The Timer 2 is clocked with the system clock divided by TMR_DIV (1, 2, 4 or 8) and can
be enabled with TRIPLE_PWM_CTRL_REG[TRIPLE_PWM_ENABLE].
T2_FREQ_CNTR determines the output frequency of the T2_PMWn output. This
counter counts down from the value stored in register TRIPLE_PWM_FREQUENCY. At
counter value 0, T2_FREQ_CNTR sets the T2_PWMn output to ‘1’ and the counter is
reloaded again.
T2_DUTY_CNTR is an up-counter that determines the duty cycle of the T2_PWMn
output signal. After the block is enabled, the counter starts from 0. If T2_DUTY_CNTR
is equal to the value stored in the respective PWMn_DUTY_CYCLE register, this resets
the T2_PWMn output to 0. T2_DUTY_CNTR is reset when
TRIPLE_PWM_FREQUENCY is 0.
Note that the value of PWMn_DUTY_CYCLE must be less or equal than
TRIPLE_PWM_FREQUENCY.
The Timer 2 is enabled/disabled by programming the
TRIPLE_PWM_CTRL_REG[TRIPLE_PWM_EN] bit.
The timing diagram of Timer 2 is shown in Figure 36
Freeze function
During RF activity it may be desirable to temporarily suppress the PWM switching noise.
This can be done by setting TRIPLE_PWM_CTRL_REG[HW_PAUSE_EN] = 1. The
effect is that whenever there is a transmission or a reception process from the Radio,
T2_DUTY_CNTR is frozen and T2_PWMx output is switched to ‘0’ to disable the
selected T2_PWM1, T2_PWM2, T2_PWM3. As soon as the Radio is idle (i.e. RX_EN or
TX_EN signals are zero), T2_DUTY_CNTR resumes counting and finalizes the
remaining part of the PWM duty cycle.
TRIPLE_PWM_CTRL_REG[SW_PAUSE_EN] can be set to ‘0’ to disable the automatic,
hardware driven freeze function of the duty counter and keep the duty cycle constant.
Note that the RX_EN and TX_EN signals are not software driven but controlled by the
BLE core hardware.