Data Sheet

ISM14585-L35 Specification
DOC-DS-14585-201807-3.0
Confidential Inventek Systems
Page 71
Figure 37 Watchdog Timer Block Diagram
The 8 bits watchdog timer is decremented by 1 every 10.24ms. The timer value can be
accessed through the WATCHDOG_REG register which is set to 255 (FF16) at reset.
This results in a maximum watchdog time-out of ~2.6s. During write access the
WATCHDOG_REG[WDOG_WEN] bits must be 0. This provides extra filtering for a
software run-away writing all ones to the WATCHDOG_REG. If the watchdog counter
reaches 0, the counter value will get a negative value by setting bit 8. The counter
sequence becomes 1, 0, 1FF16 (-1), 1FE16(-2),...1F016 (-16).
If WATCHDOG_CTRL_REG[NMI_RST] = 0, the watchdog timer will generate an NMI if
the watchdog timer reaches 0 and a WDOG reset if the counter becomes less or equal
to -16 (1F016). The NMI handler must write any value > -16 to the WATCHDOG_REG
to prevent the generation of a WDOG reset at counter value -16 after 16*10.24 =
163.8ms.
If WATCHDOG_CTRL_REG[NMI_RST] = 1, the watchdog timer generates a WDOG
reset if the timer becomes less or equal than 0.
The WDOG reset is one of the SYS (system) reset sources and resets the whole
device, including setting the WATCHDOG_REG register to 255, except for the RST pin,
the Power On reset, the HW reset and the DBG (debug module) reset. Since the HW
reset is not triggered, the SYS_CTRL_REG[REMAP_ADR0] bits will retain their value
and the Cortex-M0 will start executing again from the current selected memory at
address zero. Refer to the POR, HW and SW Reset section for an overview of the
complete reset circuit and conditions.
For debugging purposes, the Cortex-M0 Debug module can always freeze the
watchdog by setting the DHCSR[DBGKEY | C_HALT | C_DEBUGEN] control bits
(reflected by the status bit S_HALT). This is automatically done by the debug tool, e.g.
during step-by-step debugging. Note that this bit also freezes the Wake-up Timer, the
Software Timer and the BLE master clock. For additional information also see the
DEBUG_REG[DEBUGS_FREEZE_EN] mask register. The C_DEBUGEN bit is not
accessible by the user software to prevent freezing the watchdog.
In addition to the S_HALT bit, the watchdog timer can also be frozen if NMI_RST=0 and
SET_FREEZE_REG[FRZ_WDOG] is set to ‘1’. The watchdog timer resumes counting
when RESET_FREEZE_REG[FRZ_WDOG] is set to ‘1’. The
WATCHDOG_CTRL_REG[NMI_RST] bit can only be set by software and will only be
reset on a SYS reset. Note that if the system is not remapped, i.e. SysRAM is at
address 0x20000000, then a watchdog fire will trigger the BootROM code to be
executed again.