Data Sheet

ISM14585-L35 Specification
DOC-DS-14585-201807-3.0
Confidential Inventek Systems
Page 73
9.13.1 PROGRAMMABLE PIN ASSIGNMENT
The Programmable Pin Assignment (PPA) provides a multiplexing function to the I/O
pins of on-chip peripherals. Any peripheral input or output signal can be freely mapped
to any I/O port bit by setting Pxy_MODE_REG[4-0]:
0x00 to 0x1F: Peripheral IO ID (PID)
Refer to the Px_MODE_REGs for an overview of the available PIDs. Analog ADC has
fixed pin assignment in order to limit interference with the digital domain. The SWD
interface (JTAG) is mapped on P1_4 and P1_5.
Priority
The firmware has the possibility to assign the same peripheral output to more than one
pin. It is the responsibility of the user to make a unique assignment.
In case more than one input signal is assigned to a peripheral input, the left most pin in
the lowest port pin number has priority. (e.g P00_MODE_REG has priority over
P01_MODE_REG).
Direction Control
The port direction is controlled by setting:
Pxy_MODE_REG[9-8]
00 = Input, no resistors selected
01 = Input, pull-up selected
10 = Input, Pull-down selected
11 = Output, no resistors selected
In output mode and analog mode, the pull-up/down resistors are automatically disabled.
9.13.2 GENERAL PURPOSE PORT REGISTERS
The general purpose ports are selected with PID=0. The port function is accessible
through registers:
• Px_DATA_REG: Port data input/output register
• Px_SET_OUTPUT_DATA_REG: Port set output register
• Px_RESET_OUTPUT_DATA_REG: Port reset output register