Data Sheet

ISM14585-L35 Specification
DOC-DS-14585-201807-3.0
Confidential Inventek Systems
Page 74
9.13.2.1 PORT DATA REGISTER
The registers input Px_DATA_REG and output Px_DATA_REG are mapped on the
same address. The data input register (Px_DATA_REG) is a read-only register that
returns the current state on each port pin even if the output direction is selected,
regardless of the programmed PID, unless the analog function is selected (in this case it
reads 0). The ARM CPU can read this register at any time even when the pin is
configured as an output.
The data output register (Px_DATA_REG) holds the data to be driven on the output port
pins. In this configuration, writing to the register changes the output value.
9.13.2.2 PORT SET DATA OUTPUT REGISTER
Writing a 1 in the set data output register (Px_SET_OUTPUT_DATA_REG) sets the
corresponding output pin. Writing a 0 is ignored.
9.13.2.3 PORT RESET DATA OUTPUT REGISTER
Writing a 1 in the reset data output register (Px_RESET_OUTPUT_DATA_REG) resets
the corresponding output pin. Writing a 0 is ignored.
9.13.2.4 FIXED ASSIGNMENT FUNCTIONALITY
There are certain signals that have a fixed mapping on specific general purpose IOs.
This assignment is illustrated in the following table:
GPIO
QUAD DEC (Note 1)
ADC (Note 2)
P0_0
CHY_A/CHX_A/CHZ_A
ADC_0
P0_1
CHY_B/CHX_B/CHZ_B
ADC_1
P0_2
CHY_A/CHX_A/CHZ_A
ADC_2
P0_3
CHY_B/CHX_B/CHZ_B
ADC_3
P0_4
CHY_A/CHX_A/CHZ_A
P0_5
CHY_B/CHX_B/CHZ_B
P0_6
CHY_A/CHX_A/CHZ_A
P0_7
CHY_B/CHX_B/CHZ_B
P1_0
CHY_A/CHX_A/CHZ_A
P1_1
CHY_B/CHX_B/CHZ_B
P1_2
CHY_A/CHX_A/CHZ_A
P1_3
CHY_B/CHX_B/CHZ_B
• Note 1 The mapping of the Quad Decoder signals on the respective pins, is
overruled by the QDEC_CTRL2_REG[CHx_PORT_SEL] register.
• Note 2 The ADC case can be selected by the PID bit field on the respective Px port.