Data Sheet

ISM14585-L35 Specification
DOC-DS-14585-201807-3.0
Confidential Inventek Systems
Page 76
9.14.1 INPUT CHANNELS AND INPUT SCALE
The ISM14585-L35 has a multiplexer between the ADC and four specific GPIO ports
(P0_0 to P0_3). Furthermore, the ADC can also be used to monitor the battery voltage
and several internal voltages of the system (see GP_ADC_CTRL_REG).
Single-ended or differential operation is selected via bit
GP_ADC_CTRL_REG[GP_ADC_SE]. In differential mode the voltage difference
between two GPIO input ports will be converted. Via bit
GP_ADC_CTRL2_REG[GP_ADC_ATTN3X] the input scale can be enlarged by a factor
of three, as summarized in below table.
GP_ADC_ATTN3X
GP_ADC_SE
Input Channels
Input Scale
Input Limits
0
1
P0_0, P0_1, P0_2, P0_3
0 V to +1.2 V
-0.1 V to +1.3 V
0
0
[P0_0, P0_1], [P0_2, P0_3]
-1.2 V to +1.2 V
-1.3 V to +1.3 V
1
1
P0_0, P0_1, P0_2, P0_3
0 V to +3.6 V
-0.1 V to +3.45 V
1
0
[P0_0, P0_1], [P0_2, P0_3]
-
-3.6 V to +3.6 V
-3.45 V to +3.45 V
GPADC Input Channels and Voltage Scale
9.14.2 STARTING THE ADC AND SAMPLING RATE
The GPADC is a dynamic ADC and consumes no static power, except for the LDO
which consumes less than 5μA. Enabling/disabling of the ADC is triggered by
configuring bit GP_ADC_CTRL_REG[GP_ADC_LDO_EN]. After enabling the LDO, a
settling time of 20 μs is required before an AD-conversion can be started.
Each conversion has two phases: the sampling phase and the conversion phase. When
bit GP_ADC_CTRL_REG[GP_ADC_EN] is set to ‘1’, the ADC continuously tracks
(samples) the selected input voltage. Writing a '1' at bit
GP_ADC_CTRL_REG[GP_ADC_START] ends the sampling phase and triggers the
conversion phase. When the conversion is ready, the ADC resets bit GP_ADC_START
to ‘0’ and returns to the sampling phase.
The conversion itself is fast and takes approximately one clock cycle of 16 MHz, though
the data handling will require several additional clock cycles, depending on the software
code style. The fastest code can handle the data in four clock cycles of 16 MHz,
resulting to a highest sampling rate of 16 MHz/5 = 3.3 Msample/s.
At full speed the ADC consumes approximately 50μA. If the data rate is less than 100
ksample/s, the current consumption will be in the range of 5μA.