Data Sheet

ISM14585-L35 Specification
DOC-DS-14585-201807-3.0
Confidential Inventek Systems
Page 77
9.14.3 NON-IDEAL EFFECTS
Besides Differential Non-Linearity (DNL) and Integral Non-Linearity (INL), each ADC
has a gain error (linear) and an offset error (linear). The gain error of the GPADC
slightly reduces the effective input scale (up to 50 mV). The offset error causes the
effective input scale to become non-centered. The offset error of the GPADC is less
than 20 mV and can be reduced by chopping or by offset calibration.
The ADC result will also include some noise. If the input signal itself is noise free
(inductive effects included), the average noise level will be ±1 LSB. Taking more
samples and calculating the average value will reduce the noise and increase the
resolution.
With a 'perfect' input signal (e.g. if a filter capacitor is placed close to the input pin) most
of the noise comes from the low-power voltage regulator (LDO) of the ADC. Since the
DA14585 is targeted for ultra-compact applications, there is no pin available to add a
capacitor at this voltage regulator output.
The dynamic current of the ADC causes extra noise at the regulator output. This noise
can be reduced by setting bits GP_ADC_CTRL2_REG[GP_ADC_I20U] and
GP_ADC_CTRL2_REG[GP_ADC_IDYN] to ‘1’. Bit GP_ADC_I20U enables a constant
20μA load current at the regulator output so that the current will not drop to zero. Bit
GP_ADC_IDYN enables a 10μA load current during sampling phase so that the load
current during sampling and conversion phase becomes approximately the same.
9.14.4 CHOPPING
Chopping is a technique to cancel offset by taking two samples with opposite signal
polarity. This method also smooths out other non-ideal effects and is recommended for
DC and slowly changing signals.
Chopping is enabled by setting bit GP_ADC_CTRL_REG[GP_ADC_CHOP] to ‘1’.
The mid-scale value of the ADC is the 'natural' zero point of the ADC (ADC result =
511.5 = 1FF or 200 Hex = 01.1111.1111 or 10.0000.0000 Bin). Ideally this corresponds
to Vi = 1.2 V/2 = 0.6 V in single-ended mode and Vi = 0.0 V in differential mode.
If bit GP_ADC_CTRL2_REG[GP_ADC_ATTN3X] is set to ‘1’, the zero point is 3 times
higher (1.8 V single-ended and 0.0 V differential).