Data Sheet

ISM14585-L35 Specification
DOC-DS-14585-201807-3.0
Confidential Inventek Systems
Page 80
sampling capacitor. The conversion time is approximately one clock cycle of 16 MHz
(62.5 ns).
7 * ROUT * 0.2 pF - 62.5 ns < 1/fS
=> ROUT < (1 + 62.5 ns * fS) / (7 * 0.2 pF * fS)
Examples:
ROUT < 7.2 MΩ at fS = 100 kHz
ROUT < 760 kΩ at fS = 1 MHz
The inductance from the signal source to the ADC input pin must be very small.
Otherwise, filter capacitors are required from the input pins to ground (differential mode:
from pin to pin). To observe the noise level of the ADC and the voltage regulator, bit
GP_ADC_CTRL_REG[GP_ADC_MUTE] must be set to ‘1’. The noise should be less
than ±1 LSB on average, with occasionally a ±2 LSB peak value. If a higher noise level
is observed on the input channel(s), applying filter capacitor(s) will reduce the noise.
The 3x input attenuator is realized with a resistor divider network. When bit
GP_ADC_CTRL_REG2[GP_ADC_ATTN3X] is set to ‘1’, the input impedance of the
selected ADC input channel becomes 300 kΩ (typical) instead of infinite. In addition, the
resistor divider network will require more settling time in the sampling phase. The
general guideline with bit GP_ADC_ATTN3X = 1 is: select the input channel, then wait 1
μs (16 clock cycles) before starting the conversion. Only the required sampling time is
affected by the attenuator, the conversion time remains approximately one clock cycle
of 16 MHz (62.5 ns).
Note: Selecting the battery measurement channel automatically activates the 3x input
attenuator (bit GP_ADC_ATTN3X = 1). Therefore the 1 μs waiting time also applies
when measuring the battery voltage, otherwise the resulting Vbat level will be too low.
9.14.9 COMMON MODE ADJUSTMENT
The GPADC has a delay counter that can be used to add delays to several ADC control
signals. A delay of up to 32μs can be added for the bits GP_ADC_LDO_EN,
GP_ADC_START and GP_ADC_EN via registers GP_ADC_DELAY_REG and
GP_ADC_DELAY2_REG.
The reset values of these two registers are the recommended values for a correct start-
up, since it is not allowed to activate all signals at once.
To make use of the delay counter for a certain signal, the corresponding bit has to be
set in register GP_ADC_CTRL_REG and the delay counter must be enabled via bit