Data Sheet

ISM14585-L35 Specification
DOC-DS-14585-201807-3.0
Confidential Inventek Systems
Page 81
GP_ADC_DELAY_EN in register GP_ADC_CTRL2_REG. The delay counter starts
counting when the GP_ADC_START bit is programmed while the
GP_ADC_DELAY_EN bit is set. The counter is stopped after the conversion is finished.
The delay counter must be reset before reuse, which is typically only required after the
LDO was disabled. Bit GP_ADC_DELAY_EN must be made zero to reset the counter. It
is recommended to check that this bit is zero before (re)activating it.
9.14.10 Sample Rate Converter (SRC)
The SRC is a HW accelerator used to convert the sample rate of audio samples
between various interfaces. Its primary purpose is to directly connect PCM and PDM
channels while converting the rate accordingly.
Features:
• Supported conversions:
o SRC_IN (24 bits) to SRC_OUT (24 bits)
o PDM_IN (1bit) to SRC_OUT (24 bits)
o SRC_IN (24 bits) to PDM_OUT (1 bit)
• SRC_IN, SRC_OUT Sample rates 8 kHz to 192 kHz
• SNR > 100 dB
• Single Buffer I/O with DMA support
• Automatic mode to adjust sample rate to the applied frame sync (e.g. PCM_FSC)
• Manual mode to generate interrupts at the programmed sample rate. Adjustment is done
by SW based on buffer pointers
• SRC runs at 16 MHz
Figure 40 Sample Rate Converter block diagram