Data Sheet

ISM14585-L35 Specification
DOC-DS-14585-201807-3.0
Confidential Inventek Systems
Page 82
9.14.11 SRC ARCHITECTURE
9.14.11.1 I/O CHANNELS
The SRC block converts two 24 bits channels either as a stereo pair or as two mono
channels. The PCM linear data pairs are received on SRC_IN and the output is 2x24
bits left aligned on SRC_OUT. The two 1 bit PDM data inputs are received on PDM_IN
and are converted to 2x24 bits, left aligned to SRC_OUT.
9.14.11.2 I/O MULTIPLEXERS
The SRCx_IN input multiplexer (Figure 40) is controlled by APU_MUX_REG. The input
of these multiplexers either comes from the audio interfaces of from registers
SRC1_IN1_REG and SRC1_IN2_REG. The data to these register is left aligned, bits
31-8 are mapped on bits 23-0 of the SRC.
The 24 bits SRCs outputs can be read in SRC1_OUT1_REG and SRC1_OUT2_REG
and is also routed to the PCM. This input selection of these multiplexers is also
controlled by APU_MUX_REG.
9.14.11.3 INPUT AND OUTPUT SAMPLE RATE CONVERSION
Depending on the use case the Sample Rate Converter operate in either manual or
automatic conversion mode. This mode can be set in the SRC1_CTRL_REG bits
SRC_IN_AMODE and bit SRC_OUT_AMODE.
9.14.11.4 SRC CONVERSION MODES OF OPERATION
Both at the input and at the output side, the SRC can operate in two mode of operation:
• Manual mode
• Automatic mode
In manual mode, the input/output sample rate is determined by SRC1_IN_FS_REG
/SRC1_OUT_FS_REG registers.
In automatic mode, the input/output sample rate is derived from the external
synchronization signals and can be read back from SRC1_IN_FS_REG /
SRC1_OUT_FS_REG registers. When the PDM is used (input/output), the SRC
operates in automatic mode. The sample rate reported in SRC1_IN_FS_REG register is
PDM_CLK/64. Typical Use Cases of the SRC are given on the table below:.