Data Sheet

ISM14585-L35 Specification
DOC-DS-14585-201807-3.0
Confidential Inventek Systems
Page 83
9.14.11.5 DMA OPERATION
If more than one sample must be transfer to/from the CPU or the sample rate is so high
that it interrupts the CPU too often, the DMA controller must be engaged to perform the
transactions.
9.14.11.6 INTERRUPTS
After a Sample Rate Conversion, the input up-sampler and output down-sampler
generate edge triggered interrupts on SRC_IN_SYNC and SRC_OUT_SYNC to the
CPU which do not have to be cleared. Note that only one sample shall be read from or
written to a single register at a time (i.e. there are no FIFOs included).
9.14.11.7 SRC USE CASES
The Sample Rate Converter supports any sample rate between 8 kHz and 48 kHz.
Below table shows typical use cases of the Sample Rate Converter.
Use case
SRCx_IN_AMODE
DATA path
SRCx_IN_SYNC
SRCx_IN_SYNC
(out)
SRCx_OUT_AMODE
DATA path
SRCx_OUT_SYNC
SRCx_OUT_SYNC
(out)
PCM/PDM to
BLE
Automatic
PDMx_IN_DATA
PCMx_SYNC
PCMx_IN_DATA
PCMx_SYNC
Manual
SRCx_OUT_REG
up-to 192kHz
BLE to
PCM / PDM
Manual
SRCx_IN_REG
up-to 192kHz
Automatic
PDMx_IN_DATA
PCMx_SYNC
PCMx_IN_DATA
PCMx_SYNC
PCM to PCM resampler (output must be a multiple of 8 kHz)
PCM1_IN to
PCM2_OUT
Automatic
PCM1_IN
PCM1_FSC (input)
Automatic
PCM2_OUT
PCM2_FSC (output)
PCM2_IN to
PCM1_OUT
Automatic
PCM2_IN
PCM2_FSC (input)
Automatic
PCM1_IN
PCM1_FSC (output)
Table of Typical SRC use case