Data Sheet

ISM14585-L35 Specification
DOC-DS-14585-201807-3.0
Confidential Inventek Systems
Page 88
9.16.1.3 CHANNEL DELAY
The 8 PCM channels can be delayed with a maximum delay of 31x8bits using the bit
field PCM1_CTRL_REG[PCM_CH_DEL]. Note that a high delay count in combination
with a slow clock, can lead to the PCM_FSC sync occurring before all channels are
shifted in or out. The received bits of the current channel may not be properly aligned in
that case.
9.16.1.4 CLOCK GENERATION
Figure 45 shows the PCM clock generation block and the Table below, the
PCM_DIV_REG and PCM_FDIV_REG values for given PCM_FSC and PCM_CLK in
master mode. The PCM_DIV_REG[PCM_DIV] is a 12 bits field which holds the integer
part of the desired clock divider.
The fractional part of the divider is stored in the 16 bits PCM_FDIV_REG register. The
value of the register is calculated in the following way. The position of the left most '1' of
the value in binary format defines the denominator and the number of '1' bits define the
numerator of the fraction as shown in the Table below.
PCM_FDIV_REG (Hex)
PCM_FDIV_REG (Binary)
Numerator
Denominator
Fraction
0x0110
0b100010000
2
9
2/9
0x0101
0b100000001
2
9
2/9
0x1abc
0b1101010111100
8
13
8/13
0xbeef
0b1011111011101111
13
16
13/16
0xfeee
0b1111111011101110
13
16
13/16
PCM_FDIV_REG Example Calculations
Figure 45 PCM clock generation