Data Sheet

ISM14585-L35 Specification
DOC-DS-14585-201807-3.0
Confidential Inventek Systems
Page 90
9.16.1.5 DATA FORMATS
9.16.1.5.1 PCM MASTER MODE
Master mode is selected if PCM1_CTRL_REG[PCM_MASTER] = 1.
In master mode PCM_FSC is output and falls always over Channel 0. The duration of
PCM_FSC is programmable with PCM1_CTRL_REG[PCM_FSCLEN]= 1 or 8,16, 24, 32
clock pulses high. The start position is programmable with
PCM1_CTRL_REG[PCM_FSCDEL] and can be placed before or on the first bit of
channel 0.
The repetition frequency of PCM_FSC is programmable in
PCM1_CTRL_REG[PCM_FSC_DIV] to from 8-192kHz.
If master mode selected, PCM_CLK is output and provides one or two clocks per data
bit programmable in PCM1_CTRL_REG[PCM_CLK_BIT].
The polarity of the signal can be inverted with bit PCM1_CTRL_REG[PCM_CLKINV].
The PCM_CLK frequency selection is described in Section 9.14.1.4.
9.16.1.5.2 PCM SLAVE MODE
In slave mode (bit MASTER = 0) PCM_FSC is input and determines the starting point of
channel 0.
The repetition rate of PCM_FSC must be equal to PCM_SYNC and must be high for at
least one PCM_CLK cycle. Within one frame, PCM_FSC must be low for at least
PCM_CLK cycle. Bit PCM_FSCDEL sets the start position of PCM_FSC before or on
the first bit (MSB).
In slave mode PCM_CLK is input. The minimum received frequency is 256 kHz, the
maximum is 12.288MHz.
In slave mode the main counter can be stopped and resumed on a PCM1_FSC or
PCM2_FSC rising edge.