Data Sheet

ISM14585-L35 Specification
DOC-DS-14585-201807-3.0
Confidential Inventek Systems
Page 92
Settings for I2S mode:
• PCM_FSC_EDGE: 1 (all after PCM_FSC)
• PCM_FSCLEN: 4 (4x8 High, 4x8 Low)
• PCM_FSC_DEL: 0 (one bit delayed)
• PCM_CLK_INV: 1 (output on falling edge)
• PCM_CH0_DEL: 0 (no channel delay)
Figure 47 I2S Mode
TDM mode
A time is specified from the normal ‘start of frame’ condition using register bits
PCM_CH_DEL. In the left-justified TDM example illustrated in Figure 48, the left
channel data is valid PCM_CH_DEL clock cycles after the rising edge of the PCM_FSC,
and the right channel data is valid the same PCM_CH_DEL number of clock cycles after
the falling edge of the PCM_FSC.
By delaying the channels, also left and right alignment can be achieved.
Settings for TDM mode:
• PCM_FSC_EDGE: 1 (rising and falling PCM_FSC)
• PCM_FSCLEN: Master 1 to 4 Slave waiting for edge.
• PCM_FSC_DEL: 1 (no bit delay)
• PCM_CLK_INV: 1 (output on falling edge)
• PCM_CH0_DEL: Slave 0-31 (channel delay) Master 1-3