Data Sheet

4-Level FSK Modem Data Pump Page 16 of 47 MX919B PRELIMINARY INFORMATION
©2001 MX•COM, INC. www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: [phone] Doc. # 20480170.003
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4.5.2.1 Command Register B7: AQSC - Acquire Symbol Clock
This bit has no effect in transmit mode.
In receive mode, when a byte with the AQSC bit set to '1' is written to the Command Register, and TASK is
not set to RESET, it initiates an automatic sequence designed to achieve symbol timing synchronization with
the received signal as quickly as possible. This involves setting the Phase Locked Loop of the received bit
timing extraction circuits to its widest bandwidth, then gradually reducing the bandwidth as timing
synchronization is achieved, until it reaches the 'normal' value set by the PLLBW bits of the Control Register.
Setting this bit to '0' (or changing it from '1' to '0') has no effect, however; the acquisition sequence will be re-
started every time a byte written to the Command Register has the AQSC bit set to '1'.
The use of the symbol clock acquisition sequence is described in Section 5.3.
4.5.2.2 Command Register B6: AQLEV - Acquire Receive Signal Levels
This bit has no effect in transmit mode.
In receive mode, when a byte with the AQLEV bit set to '1' is written to the Command Register and TASK is
not set to RESET, it initiates an automatic sequence designed to measure the amplitude and DC offset of the
received signal as rapidly as possible. This sequence involves setting the measurement circuits to respond
quickly at first, then gradually increasing their response time, therefore improving the measurement accuracy,
until the 'normal' value set by the LEVRES bits of the Control Register is reached.
Setting this bit to '0' (or changing it from '1' to '0') has no effect, however; the acquisition sequence will be re-
started every time a byte written to the Command Register has the AQLEV bit set to '1'.
The use of the level measurement acquisition sequence (AQLEV) is described in Section 5.3.
4.5.2.3 Command Register B5: CRC
This bit allows the user to select between two different initial states of the CRC1 and CRC2 checksum
generators. When this bit is set to ‘0’, the CRC generators are initialized to ‘all ones’ as for CCITT X25 CRC
calculations. When this bit is set to ‘1’, the CRC generators are initialized to ‘all zeros’. Setting this bit to ‘0’
provides compatibility with the MX919, a prior member of the MX919 device family. Other systems may set
this bit as required. Note: This bit must be set correctly every time the Command Register is written to.
4.5.2.4 Command Register B4: TXIMP - Tx Level/Impulse Shape
This bit allows the user to choose between two transmit symbol waveform shapes as described in
Section 4.7. Note: This bit must be set correctly every time the Command Register is written to.
4.5.2.5 Command Register B3 - Reserved
This bit should always be set to '0'.
4.5.2.6 Command Register B2, B1, B0: TASK
Operations such as transmitting or receiving a data block are treated by the modem as 'tasks' and are
initiated when the µC writes a byte to the Command Register with the TASK bits set to anything other than
the 'NULL' code.
The µC should not write a task (other than NULL or RESET) to the Command Register or write to or read
from the Data Buffer when the BFREE (Buffer Free) bit of the Status Register is '0'.
Different tasks apply in receive and transmit modes.
When the modem is in transmit mode, all tasks other than NULL or RESET instruct the modem to transmit
data from the Data Buffer, formatting it as required. The µC should therefore wait until the BFREE (Buffer
Free) bit of the Status Register is '1', before writing the data to the Data Block Buffer, then it should write the
desired task to the Command Register. If more than 1 byte needs to be written to the Data Block Buffer, byte
number 0 of the block should be written first.
Once the byte containing the desired task has been written to the Command Register, the modem will:
Set the BFREE (Buffer Free) bit of the Status Register to '0'.
Take the data from the Data Block Buffer as quickly as it can - transferring it to the Interleave Buffer for
eventual transmission. This operation will start immediately if the modem is 'idle' (i.e. not transmitting data
from a previous task), otherwise it will be delayed until there is sufficient room in the Interleave Buffer.
Once all of the data has been transferred from the Data Block Buffer, the modem will set the BFREE and IRQ
bits of the Status Register to '1', (causing the chip
IRQ output to go low if the IRQEN bit of the Mode Register
has been set to '1') to tell the µC that it may write new data and the next task to the modem.
This lets the µC write the next task and its associated data to the modem while the modem is still transmitting
the data from its previous task.