Data Sheet
4-Level FSK Modem Data Pump Page 20 of 47 MX919B PRELIMINARY INFORMATION
©2001 MX•COM, INC. www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
4.5.2.15 TIB: Transmit Intermediate Block
This task takes 12 bytes of data from the Data Block Buffer, updates the 4-byte CRC2 checksum for inclusion
in the 'Last' block, translates the 12 data bytes to 4-level symbols (with FEC), interleaves the symbols, and
transmits the result as a formatted 'Intermediate' Block.
Once the modem has read the data bytes from the Data Block Buffer, the BFREE and IRQ bits of the Status
Register will be set to '1'.
4.5.2.16 TLB: Transmit Last Block
This task takes 8 bytes of data from the Data Block Buffer, updates and appends the 4-byte CRC2 checksum,
translates the resulting 12 bytes to 4-level symbols (with FEC), interleaves the symbols, and transmits the
result as a formatted 'Last' Block.
Once the modem has read the data bytes from the Data Block Buffer, the BFREE and IRQ bits of the Status
Register will be set to '1'.
4.5.2.17 T4S: Transmit 4 Symbols
This command is similar to T24S but takes only one byte from the Data Block Buffer, transmitting it as four 4-
level symbols.
4.5.2.18 RESET: Stop any current action
This 'task' takes effect immediately, and terminates any current action (task, AQSC or AQLEV) the modem
may be performing and sets the BFREE bit of the Status Register to '1', without setting the IRQ bit. It should
be used when V
DD
is applied, to set the modem into a known state.
Note: Due to delays in the transmit filter, it will take several symbol times for any change to appear at the
TXOUT pin.
4.5.2.19 Task Timing
The following table and figures describe the duration of tasks and timing sequences for Tx and Rx operation.
Task
Time
(symbol times)
t
1
Modem Idle state. Time from writing first task to application of first
transmit bit to Tx RRC filter.
Any 1 to 2
t
2
Time from application of first symbol of the task to the Tx RRC filter
until BFREE goes to a logic ‘1’.
T24S
THB/TIB/TLB
T4S
5
16
0
t
3
Time to transmit all symbols of the task.
T24S
THB/TIB/TLB
T4S
24
66
4
t
4
Max time allowed from BFREE going to a logic ‘1’ (high) for next task
(and data) to be written to modem.
T24S
THB/TIB/TLB
T4S
18
49
3
t
5
Time to receive all symbols of task.
SFS
SFSH
RHB/RILB
R4S
24 (minimum)
90 (minimum)
66
4
t
6
Maximum time between first symbol of task entering the de-interleave
circuit and the task being written to modem.
SFS
SFSH
RHB/RILB
R4S
21
21
49
3
t
7
Maximum time from the last bit of the task entering the de-interleave
circuit to BFREE going to a logic ‘1’ (high).
Any 1