Data Sheet
4-Level FSK Modem Data Pump Page 21 of 47 MX919B PRELIMINARY INFORMATION
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from Task 2
from Task 3
from Task 1
t
1
t
2
Task to Command Register
Data to Data Block Buffer
t
3
t
4
Modem Tx Output
12
1 2
Symbols to RRC Filter
3
IBEMPTY Bit
BFREE Bit
3
t
2
t
2
t
3
t
3
t
4
t
4
Figure 11: Transmit Task Timing Diagram
for Task 2 for Task 3for Task 1
Task to Command Register
Data from Data Block Buffer
Modem Rx Input
12
1
2
Symbols to De-Interleave
Circuit
3
BFREE Bit
3
t
5
t
6
t
7
t
5
t
5
t
5
t
6
t
6
t
7
t
7
Figure 12: Receive Task Timing Diagram
4.5.2.20 RRC Filter Delay
The previous task timing figures are based on the signal at the input to the RRC filter (in transmit mode) or the
input to the de-interleave buffer (in receive mode). There is an additional delay of about 8 symbol times
through to the RRC filter in both transmit and receive modes, as illustrated below:
Delay from Rx Input
(from FM discriminator)
to interpreted data in
internal buffer.
RX Symbol to De-Interleave Buffer
Tx Symbol at TXOUT pin / Rx Symbol from FM discriminator
Symbol-times
Tx Symbol to RRC Filter
Delay from Tx Input
symbol to TXOUT
response.
Figure 13: RRC Low Pass Filter Delay