Data Sheet

4-Level FSK Modem Data Pump Page 22 of 47 MX919B PRELIMINARY INFORMATION

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4.5.3 Control Register

This 8-bit write-only register controls the modem's symbol rate, the response times of the receive clock

extraction, signal level measurement circuits, and the Frame Sync pattern recognition tolerance to inexact

matches.

76543210

Control Register

FSTOL

LEVRES PLLBW

CKDIV

4.5.3.1 Control Register B7, B6: CKDIV - Clock Division Ratio

These bits control a frequency divider driven from the clock signal present at the XTAL pin, therefore

determining the nominal symbol rate. Because each symbol represents two bits, bit rates are 2x the symbol

rates. The table below shows how symbol rates of 2400/4800/9600 symbols/sec (4800/9600/19200bps) may

be obtained from common Xtal frequencies:

Xtal Frequency (MHz)

2.4576 4.9152 9.8304

B7 B6

Division Ratio:

Xtal Frequency/Symbol Rate

Symbol Rate (symbols/sec) / Bit Rate

(bps)

0 0 512 4800/9600 9600/19200

0 1 1024 2400/4800 4800/9600 9600/19200

1 0 2048 2400/4800 4800/9600

1 1 4096 2400/4800

4.5.3.2 Control Register B5, B4: FSTOL - Frame Sync Tolerance to Inexact Matches

These two bits have no effect in transmit mode. In receive mode, they define the maximum number of

mismatches allowed during a search for the Frame Sync pattern:

B5 B4 Mismatches allowed

0 0 0

0 1 2

1 0 4

1 1 6

Note: A single 'mismatch' is defined as the difference between two adjacent symbol levels, thus if the symbol

'+1' were expected, then received symbol values of '+3' and '-1' would count as 1 mismatch, a received

symbol value of '-3' would count as 2 mismatches. A setting of '4 mismatches' is recommended for

normal use.