Data Sheet

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4-Level FSK Modem Data Pump Page 26 of 47 MX919B PRELIMINARY INFORMATION

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4.5.5 Status Register

This register may be read by the µC to determine the current state of the modem.

76543210

Status Register

IRQ

DIBOVFBFREE

Reserved

IBEMPTY CRCERR

4.5.5.1 Status Register B7: IRQ - Interrupt Request

This bit is set to '1' by:

The Status Register BFREE bit going from '0' to '1', unless this is caused by a RESET task or by a

change to the Mode Register

TX RX/ or PSAVE bits

or The Status Register IBEMPTY bit going from '0' to '1', unless this is caused by a RESET task or by

changing the Mode Register

TX RX/ or PSAVE bits.

The Status Register DIBOVF bit going from '0' to '1'.

The IRQ bit is cleared to '0' immediately after a read of the Status Register.

If the IRQEN bit of the Mode Register is '1', then the chip

IRQ output will be pulled low (V

) when the IRQ

bit is set to '1', and will go high impedance when the Status Register is read.

4.5.5.2 Status Register B6: BFREE - Data Block Buffer Free

This bit reflects the availability of the Data Block Buffer and is cleared to '0' when a task other than NULL or

RESET is written to the Command Register.

In transmit mode, the BFREE bit will be set to '1' (also setting the Status Register IRQ bit to '1') by the modem

when the modem is ready for the µC to write new data to the Data Block Buffer and the next task to the

Command Register.

In receive mode, the BFREE bit is set to '1' (also setting the Status Register IRQ bit to '1') by the modem

when it has completed a task and any data associated with that task has been placed into the Data Block

Buffer. The µC may then read that data and write the next task to the Command Register.

The BFREE bit is also set to '1' - but without setting the IRQ bit - by a RESET task or when the Mode Register

TX RX/ or PSAVE bits are changed.

4.5.5.3 Status Register B5: IBEMPTY - Interleave Buffer Empty

In transmit mode, this bit will be set to '1' - also setting the IRQ bit - when less than two symbols remain in the

Interleave Buffer. Any transmit task written to the modem after this bit goes to '1' will be too late to avoid a

gap in the transmit output signal.

The bit is also set to '1' by a RESET task or by a change of the Mode Register

TX RX/ or PSAVE bits, but in

these cases the IRQ bit will not be set.

The bit is cleared to '0' within one symbol time after a task other than NULL or RESET is written to the

Command Register.

Note: When the modem is in transmit mode and the Interleave Buffer is empty, a mid-level (halfway between

'+1' and '-1') signal will be sent to the RRC filter.

In receive mode this bit will be '0'.

4.5.5.4 Status Register B4: DIBOVF - De-Interleave Buffer Overflow

In receive mode this bit will be set to '1' - also setting the IRQ bit - when a RHB, RILB or R4S task is written to

the Command Register too late to allow continuous reception.

The bit is cleared to '0' immediately after reading the Status Register, by writing a RESET task to the

Command Register or by changing the

TX RX/ or PSAVE bits of the Mode Register.

In transmit mode this bit will be '0'.