Data Sheet
4-Level FSK Modem Data Pump Page 27 of 47 MX919B PRELIMINARY INFORMATION
©2001 MX•COM, INC. www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
4.5.5.5 Status Register B3: CRCERR - CRC Checksum Error
In receive mode, this bit will be updated at the end of a SFSH, RHB or RILB task to reflect the result of the
receive CRC check. '0' indicates that the CRC was received correctly, '1' indicates an error.
Note: This bit should be ignored when an 'Intermediate' block (which does not have an integral CRC) is
received.
The bit is cleared to '0' by a RESET task or by changing the
TX RX/ , or PSAVE bits of the Mode Register. In
transmit mode this bit is '0'.
4.5.5.6 Status Register B2, B1, B0
These bits are reserved for future use.
4.5.6 Data Quality Register
In receive mode, the MX919B continually measures the 'quality' of the received signal, by comparing the
actual received waveform over the previous 64 symbol times against an internally generated 'ideal' 4-level
FSK baseband signal.
The result is placed into bits 3-7 of the Data Quality Register for the µC to read at any time, bits 0-2 being
always set to '0'. Figure 15 shows how the value (0-255) read from the Data Quality Register varies with
received signal-to-noise ratio:
7
5
9111315
0
50
100
150
200
250
DQ
S/N dB (noise in 2 x symbol-rate bandwidth)
Figure 15: Typical Data Quality Reading vs S/N
The Data Quality readings are only valid when the modem has successfully acquired signal level and timing
lock for at least 64 symbol times. It is invalid when an AQSC or AQLEV sequence is being performed or
when the LEVRES setting is 'Lossy Peak Detect'. A low reading will be obtained if the PLLBW bits are set to
'Wide' or if the received signal waveform is distorted in any significant way.
Section 5.6 describes how monitoring the Data Quality reading can help improve the overall system
performance in some applications.
4.6 CRC, FEC, and Interleaving
4.6.1 Cyclic Redundancy Codes
4.6.1.1 CRC1
This is a sixteen-bit CRC check code contained in bytes 10 and 11 of the Header Block, which provides error
detection coverage for the Header Block of a message. It is calculated by the modem from the first 80 bits of
the Header Block (Bytes 0 to 9 inclusive) using the generator polynomial:
x
16
+ x
12
+ x
5
+ 1