Data Sheet

4-Level FSK Modem Data Pump Page 33 of 47 MX919B PRELIMINARY INFORMATION

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.

5.2 Receive Frame Example

The operations needed to receive a single Frame consisting of Symbol and Frame Sync sequences and one

each Header, Intermediate and Last blocks are shown below;

1. Ensure that the Control Register has been loaded with suitable CKDIV, FSTOL, LEVRES and PLLBW

values, and that the IRQEN bit of the Mode Register is '1', the

TX RX/ PSAVE, and RXEYE bits are '0',

and the INVSYM bit is set appropriately.

2. Wait until the received carrier has been present for at least 8 symbol times (see Section 5.3).

3. Read the Status Register to ensure that the BFREE bit is '1'.

4. Write a byte containing a SFSH task and with the AQSC and AQLEV bits set to '1' to the Command

5. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1'

and the CRCERR and DIBOVF bits should be '0'.

6. Check that the CRCERR bit of the Status Register is '0' and read 10 Header Block bytes from the Data

Block Buffer.

7. Write a RILB task to the Command Register.

8. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1'

and the DIBOVF bit '0'.

9. Read 12 Intermediate Block bytes from the Data Block Buffer.

10. Write a RILB task to the Command Register.

11. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1'

and the DIBOVF bit '0'.

12. Check that the CRCERR bit of the Status Register is '0' and read the 8 Last Block bytes from Data

Buffer.

Figure 21 and Figure 22 illustrate the host µC routines needed to receive a single Frame consisting of Symbol

and Frame Sync patterns, a Header Block, any number of Intermediate blocks and one Last block. It is

assumed that the Rx Interrupt Service Routine Figure 22 is called when the MX919B’s

IRQ output goes low.