User Manual

SECTION 1: THEORY OF OPERATION
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Receiver Injection
This displays a serial data input/output interface, synthesizer, and VCO. The I/O interface circuitry
accepts clock, serial data, and enable signals from the System Controller Board via terminal block TB1. A
lock detect (LD) status output is returned to the System Controller Board from the synthesizer. U1 is a
hex Schmidt Trigger inverter, which squares up incoming signals for reliable operation of the synthesizer
chip. This is necessary because of a cable run between the two (2) boards.
The main section of this board is synthesizer chip (U2). The device contains the key components of a
phase locked loop (PLL), including a 1.1 GHz prescaler, programmable divider, and phase detector. In
operation, the desired frequency is loaded into U2 as a clocked serial bit stream via the CLK and DATA/I
inputs. The lock detection circuitry consists of inverters U1E/U1F, diode CR1, and resistor R4. When the
synthesizer is in lock, the LD pin on U2 is high, making the LD output on terminal block TB1 high. The
EXC LD input on TB1 routes the lock detect output from the Exciter Board through diode CR1, and out
through LD. This configuration tells the CPU on the System Controller Board that it is acceptable to
process received data, or to key the transmitter when LD is high. Otherwise, if a fault in either synthesizer
prevents a lock, receive and transmit operation will be inhibited.
Other items of interest include a programming switch and serial data output. Switch (JMP1) may be used
to program the firmware configuration inside chip U2. The system controller board performs programming
so a jumper is installed in the LNVCC (operation) position instead. The EXT DATA output on block TB1
sends frequency programming data to the transmitter synthesizer on the Exciter Board.
The injection signal is generated by module U7. This device is an RF oscillator with buffered outputs.
The voltage is generated by the phase detector output (PD/O) of U2, which drives a loop filter consisting
of R5, C8, C5, R3 and C9. The filter integrates the pulses, which normally appear on PD/O into a smooth
DC control signal for the oscillator.
This section displays the DC power supplies, frequency reference, and RF output circuitry. Regulator
VR1 provides 9 volts DC for U7, and RF amplifier (U6). Regulator (VR2) provides a low noise 5-volt DC
output for inverter (U1), synthesizer (U2), and reference (Y1).
Reference module (Y1) provides a high-stability 12 MHz reference frequency. Y1 is a voltage controlled,
temperature controlled crystal oscillator (VCTCXO). This device also has a VC input which accepts a
control voltage from pot R10. The pot permits a slight shift in the reference frequency which enables the
three (3) receivers to be tuned precisely to the assigned receive frequency. A diode (CR2) provides
additional voltage regulation, improving the frequency stability of reference Y1.
The RF output circuitry consists of RF amplifier (U6), and power splitters (U5, U3, and U4). U6 increases
the signal level to correct for losses in the splitters. One output drives splitter U5, which provides local
oscillator injection for receivers 2 and 3. The other output drives splitter (U4), which drives receiver 1 and
the PLL_FEEDBACK input on chip U2.
Exciter Board
This section displays the input/output interface, transmitter keying, and power supply circuitry. The
input/output interface is built around terminal block (TB1) and Schmidt Trigger inverters (U2). Incoming
clock, serial data, and chip select signals on block TB1 are squared up by U2. Then they are sent to the
appropriate inputs on the transmitter synthesizer (U9). The EXCDATA source comes from the receive
synthesizer on the Injection Synthesizer Board. A Schmidt Trigger chip is used here because of a cable
ran to the System Controller Board. The synthesizer returns a lock detect output to the Injection
Synthesizer Board via U1 and EXCLD.