User's Manual

F32700N25.doc Page 6
 A Supervisor Control Chip (U25) provides power-on reset.
 The clock controls microcontroller operation and is generated by crystal Y3 and a
Pierce oscillator circuit (inside the U30-microcontroller).
 The latch (U28) decodes low order address bits (A0-A7) from the address/data bits
(AD0-AD7). It is controlled by Address Latch Enable (ALE) output of U30 and the
bits are used by the modem.
 A 512Kx8 Static RAM Chip (U31) provides temporary storage of the radio’s
configuration data facilitating the technician with access to make changes.
 Control logic is also an important part in the microcontroller section. The RAM chip
select (RAMCS*) and modemchip select (MODEMCS*) command lines are created
by U26A, U27BCD, and U44ABC. These gates decode four (4) high order address
bits (A11-A15). The RAM is addressed by five (5) memory addresses (MA14-MA18)
bits decoded by U26D, U27A, and U24. This logic decodes port address bits (PA14-
PA18) to produce memory address bits (MA14-MA18) for the RAM chip.
Input/Output
Input/output components convert serial and handshake data from the modem section to
RS232 levels, and vice-versa. Chip U22 is an RS232 transmitter and receiver. It
converts data in 5-volt logic form to data in +/-12-volt form, as required by the RS232
standard. A charge pump power supply on the chip converts the +5-volt DC logic power
on pin 26 to the +12-volt and –12-volt levels required. Capacitors C106-C109 generate
these voltages by a charge pump. These values determine the operating voltages.
U42 is a full duplex 10base-T Ethernet controller which includes physical and MAC layer
of the protocol. Transformer T1 is the interface between analog 10 base-T signal from
the RJ45 connector and the Ethernet controller, this analog signal is then converted to
parallel data for driving the FSK modem.
Modem
The single-chip modem circuit converts parallel data to an analog audio waveform for
transmission and analog audio from a receiver to parallel data. In addition to the
modem functions, the chip provides forward error detection and correction (FEC), bit
interleaving and Viterbi Soft Decision Algorithms for more robust data communications.