User's Manual

Table Of Contents

Appendix

A–4 AJ4310 | 2019-08-13

Main MB CPU Version Version of the MB CPU of Main FPGA No

MCU Version Version of the firmware of MCU No

Arm Version Version of the App of ARM No

Kernel Version Version of the Kernel of ARM No

Inner Subflow Sub work-flow Yes

Prep CapMode Reserved No

Self CapEnable Reserved Yes

Self Cap Span Time Should not be modified; keep the original value Yes

Trigger Mode Trigger mode Yes

Sequence Interval Time Should not be modified; keep the original value Yes

Set Delay Time Exposure window for Freesync mode Yes

Exp Window Time Exposure Window for Software/Inner mode, the

value should not be larger than 10s

Yes

Acquire Delay Time Reserved Yes

Integrate Time Should not be modified; keep the original value Yes

Src Port Port number for detector No

Src IP IP address for detector Yes

Src MAC MAC address for detector Yes

Dest Port Port number for PC No

Dest IP IP address for detector No

Self Clear Enable Related to Prep CapMode, the value should be

configured as On if Prep CapMode is configured

as PrepCapMode_ClearAcq. Otherwise, the value

should be Off

If the Trigger Mode is Software/Inner, the value

should be On

Yes

Self Clear Span Time Should not be modified; keep the original value Yes

Parameter Description Can be Modified