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® Rabbit 3000® Microprocessor User’s Manual 019–0108 • 040731–O
Rabbit 3000 Microprocessor User’s Manual Part Number 019-0108 • 040731–O • Printed in U.S.A. ©2002–2004 Rabbit Semiconductor • All rights reserved. Rabbit Semiconductor reserves the right to make changes and improvements to its products without providing notice. Trademarks Rabbit and Rabbit 3000 are registered trademarks of Rabbit Semiconductor. Dynamic C is a registered trademark of Z-World, Inc.
TABLE OF CONTENTS Chapter 1. Introduction 1 1.1 Features and Specifications Rabbit 3000..............................................................................................2 1.2 Summary of Rabbit 3000 Advantages ..................................................................................................6 1.3 Differences Rabbit 3000 vs. Rabbit 2000 .............................................................................................7 Chapter 2. Rabbit 3000 Design Features 9 2.
3.5 Interrupt Structure .............................................................................................................................. 44 3.5.1 Interrupt Priority ........................................................................................................................ 44 3.5.2 Multiple External Interrupting Devices ..................................................................................... 46 3.5.3 Privileged Instructions, Critical Sections and Semaphores ...........
8.5 Memory Bank Control Registers ......................................................................................................120 8.5.1 Optional A16, A19 Inversions by Segment (/CS1 Enable) .....................................................121 8.6 Allocation of Extended Code and Data ............................................................................................123 8.7 Instruction and Data Space Support................................................................................
Chapter 14. Rabbit 3000 Clocks 209 14.1 Low-Power Design......................................................................................................................... 210 Chapter 15. EMI Control 211 15.1 Power Supply Connections and Board Layout .............................................................................. 212 15.2 Using the Clock Spectrum Spreader .............................................................................................. 212 Chapter 16.
19.16 19.17 19.18 19.19 Block Move Instructions...............................................................................................................256 Control Instructions - Jumps and Calls.........................................................................................257 Miscellaneous Instructions ...........................................................................................................257 Privileged Instructions ........................................................
Rabbit 3000 Microprocessor
1. INTRODUCTION Rabbit Semiconductor was formed expressly to design a a better microprocessor for use in small and medium-scale controllers. The first microprocessor was the Rabbit 2000. The second microprocessor, now available, is the Rabbit 3000. Rabbit microprocessor designers have had years of experience using Z80, Z180, and HD64180 microprocessors in small controllers. The Rabbit shares a similar architecture and a high degree of compatibility with these microprocessors, but it is a vast improvement.
1.1 Features and Specifications Rabbit 3000 • 128-pin LQFP package. Operating voltage 1.8 V to 3.6 V. Clock speed to 54+ MHz. All specifications are given for both industrial and commercial temperature and voltage ranges. Rabbit microprocessors are low-cost. • Industrial specifications are for 3.3 V ±10% and a temperature range from -40°C to +85°C. Modified commercial specifications are for a voltage variation of 5% and a temperature range from -40°C to 70°C.
A Rabbit that is slaved to a master processor can operate entirely with volatile RAM, depending on the master for a cold program boot. • There are 56 parallel I/O lines (shared with serial ports). Some I/O lines are timer synchronized, which permits precisely timed edges and pulses to be generated under combined hardware and software control. Pulse-width modulation outputs are implemented in addition to the timer-synchronization feature (see below).
• A built-in clock doubler allows ½-frequency crystals to be used. • The built-in main clock oscillator uses an external crystal or a ceramic resonator. Typical crystal or resonator frequencies are in the range of 1.8 MHz to 30 MHz. Since precision timing is available from the separate 32.768 kHz oscillator, a low-cost ceramic resonator with ½ percent error is generally satisfactory. The clock can be doubled or divided down to modify speed and power dynamically.
Data Buffer CLK /WDTOUT STATUS SMODE1 SMODE0 /BUFEN /IORD /IOWR /RESET RESOUT D[7:0] External Interface CPU XTALA1 XTALA2 Memory Management/ Control Spectrum Spreader Clock Doubler Fast Oscillator Global Power Save & Clock Distribution (8 bits) Address Buffer ADDRESS BUS A[19:0] Timer A Memory Chip Interface /CS2, /CS1, /CS0 /OE1, /OE0 /WE1, /WE0 Parallel Ports Port A PA [7:0] Port B PB[7:0] Port C PC[7:0] Port D PD[7:0] Port E PE[7:0] Port F PF[7:0] Port G PG[7:0] Se
1.2 Summary of Rabbit 3000 Advantages • The glueless architecture makes it is easy to design the hardware system. • There are a lot of serial ports and they can communicate very fast. • Precision pulse and edge generation is a standard feature. • EMI is at extremely low levels. • Interrupts can have multiple priorities. • Processor speed and power consumption are under program control.
1.3 Differences Rabbit 3000 vs. Rabbit 2000 For the benefit of readers who are familiar with the Rabbit 2000 microprocessor the Rabbit 3000 is contrasted with the Rabbit 2000 in the table below. Feature Rabbit 3000 Rabbit 2000 Maximum clock speed 54 MHz 30 MHz Maximum crystal frequency main oscillator (may be doubled internally) 30 MHz 32 MHz 32.768 kHz crystal oscillator External Internal Maximum operating voltage 3.6 V 5.5 V Maximum I/O input voltage 5.5 V 5.5 V 2 mA/MHz @ 3.
Feature Serial ports with support for SDLC/HDLC IrDA communications Maximum asynchronous baud rate Input capture unit 8 Rabbit 3000 Rabbit 2000 2 None clock speed/8 clock speed/32 2 None Rabbit 3000 Microprocessor
2. RABBIT 3000 DESIGN FEATURES The Rabbit 3000 is an evolutionary design. The processor and instruction set are nearly identical to the immediate predecessor processor, the Rabbit 2000. Both the Rabbit 3000 and the Rabbit 2000 follow in broad outline the instruction set and the register layout of the Z80 and Z180. Compared to the Z180 the instruction set has been augmented by a substantial number of new instructions.
2.1 The Rabbit 8-bit Processor vs. Other Processors The Rabbit 3000 processor has been designed with the objective of creating practical systems to solve real world problems in an economical fashion. A cursory comparison of the Rabbit 3000 compared to other processors with similar capabilities may miss certain Rabbit strong points. • The Rabbit is a processor that can be used to build a system in which EMI is nearly absent, even at clock frequencies in excess of 40 MHz.
The Rabbit is an 8-bit processor with an 8-bit external data bus and an 8-bit internal data bus. Because the Rabbit makes the most of its external 8-bit bus and because it has a compact instruction set, its performance is as good as many 16-bit processors. We hesitate to compare the Rabbit to 32-bit processors, but there are undoubtedly occasions where the user can use a Rabbit instead of a 32-bit processor and save a vast amount of money. Many Rabbit instructions are 1 byte long.
important for RS-485 communication because a half duplex line driver cannot have the direction of transmission reversed until the last data bit has been sent. In many UARTs, including those on the Z180, it is difficult to generate an interrupt after the last bit is sent. A so called address bit can be transmitted as either high or low after the last data bit. The address bit, if used, is followed by a high stop bit. This facility can be used to transmit 2 stop bits or a parity bit if desired.
2.2.5 Parallel I/O There are 56 parallel input/output lines divided among seven 8-bit ports designated A through G. Most of the port lines have alternate functions, such as serial data or chip select strobes. Parallel Ports D, E, F, and G have the capability of timer-synchronized outputs. The output registers are cascaded as shown in Figure 2-1. Output Port Load Data Load Clock Timer Clock Figure 2-1.
2.2.6 Slave Port The slave port is designed to allow the Rabbit to be a slave to another processor, which could be another Rabbit. The port is shared with Parallel Port A and is a bidirectional data port. The master can read any of three registers selected via two select lines that form the register address and a read strobe that causes the register contents to be output by the port. These same registers can be written as I/O registers by the Rabbit slave.
2.2.7 Auxiliary I/O Bus The Rabbit 3000 instruction set supports memory access and I/O access. Memory access takes place in a 1 megabyte memory space. I/O access takes place in a 64K I/O space. In a traditional microprocessor design the same address and data lines are used for both memory and I/O spaces. Sharing address and data lines in this manner often forces compromises or makes design more complicated.
perclk perclk Timer A System A1 A2 perclk/2 Serial E Serial F A3 Serial A A4 Serial B Input Capture A8 A5 Serial C A9 A10 A6 PWM Quadrature Decode Serial D A7 Timer A1 perclk/2 10-bit counter compare perclk/8 10 bits Timer_B1 match reg Control Timer Synchronized outputs Timer B System match preload Timer_B2 match reg match preload Figure 2-4. Rabbit Timers A and B 2.2.9 Input Capture Channels The input capture channels are used to determine the time at which an event takes place.
and stop condition, for example a rising edge could be the start condition and a falling edge the stop condition. However, optionally, the start and stop condition can be input from separate pins. The input capture channels can be used to measure the width of fast pulses. This is done by starting the counter on the first edge of the pulse and capturing the counter value on the second edge of the pulse.
length of the pulses. When the duty cycle is greater then 1/1024 the pulses are spread into groups distributed 256 counts apart in the 1024 frame. The pulse width modulation outputs can be passed through a filter and used as a 10-bit D/A converter. The outputs can also be used to directly drive devices that have intrinsic filtering such as motors or solenoids. 2.2.
reset pin, and to a programmable output pin that is used to signal the PC that attention is needed. With proper precautions in design and software, it is possible to use Serial Port A as both a programming port and as a user-defined serial port, although this will not be necessary in most cases. Rabbit Semiconductor supports the use of the standard programming port and the standard programming cable as a diagnostic and setup port to diagnosis problems or set up systems in the field. 2.3.
20 Rabbit 3000 Microprocessor
3. DETAILS ON RABBIT MICROPROCESSOR FEATURES 3.1 Processor Registers The Rabbit’s registers are nearly identical to those of the Z180 or the Z80. The figure below shows the register layout. The XPC and IP registers are new. The EIR register is the same as the Z80 I register, and is used to point to a table of interrupt vectors for the externally generated interrupts.
The Rabbit (and the Z80/Z180) processor has two accumulators—the A register serves as an 8-bit accumulator for 8-bit operations such as ADD or AND. The 16-bit register HL register serves as an accumulator for 16-bit operations such as ADD HL,DE, which adds the 16bit register DE to the 16-bit accumulator HL. For many operations IX or IY can substitute for HL as accumulators. The register marked F is the flags register or status register.
3.2 Memory Mapping Although the Rabbit memory mapping scheme is fairly complex, the user rarely needs to worry about it because the details are handled by the Dynamic C development system. Except for a handful of special instructions (see Section 19.5, “16-bit Load and Store 20bit Address”.), the Rabbit instructions directly address a 64K data memory space.
10000 85 XPC register 80 STACKSEG register 79 DATASEG register 0E000 85 93000 0D000 80 8D000 10000 XPC segment E000 stack segment D000 data segment D 7 SEGSIZE register 07000 79 80000 7000 root segment 07000 0000 16-bit address space 00000 20-bit address space Figure 3-3. Example of Memory Mapping Operation The names given to the segments in the figure are evocative of the common uses for each segment.
the root segment or it may contain data variables. The stack segment is normally 4K long and it holds the system stack. The XPC segment is normally used to execute code that is not stored in the root segment or the data segment. Special instructions support executing code that is visible in the XPC segment. The memory interface unit receives the 20-bit addresses generated by the memory-mapping unit. The memory interface unit conditionally modifies address lines A16, A18 and A19.
3.2.1 Extended Code Space A crucial element of the Rabbit memory mapping scheme is the ability to execute programs containing up to a megabyte of code in an efficient manner. This ability is absent in a pure 16-bit address processor, and it is poorly supported by the Z180 through its memory mapping unit. On paged processors, such as the 8086, this capability is provided by paging the code space so that the code is stored in many separate pages.
than the XPC segment, can call other code in the root using short jumps and calls. Code in the XPC segment can also call code in the root using short jumps and calls. However, a long call must be used when code in the XPC segment is called. Functions located in the root have an efficiency advantage because a long call and a long return require 32 clocks to execute, but a short call and a short return require only 20 clocks to execute. The difference is small, but significant for short subroutines.
fetching an instruction from memory and fetching or storing data in memory. When enabled separate I and D space make available the combined root and data segment, typically 52k bytes for root code in the I space. In the D space, the root code segment part of the D space is typically used for constant data mapped to flash memory while the data segment part of the D space is used for variable data mapped to RAM.
not have split I and D space and memory accesses to these segments do not distinguish between I and D space. The advantage of having more root code space is that root code executes faster because short calls using a 16 bit address are used to call it. This compares to long calls that have a 20 bit address for extended code.
Stack Segment used as data window Data Segment used as data window Stacks in data segment Data (RAM) Root Segment mapped to RAM has both root code and data. Root Code (flash) Stack Segment used for stack Data (RAM) Root Code (RAM) Using Stack Segment for a Data Window Using Data Segment for a Data Window (Code must be copied to RAM on startup.) Figure 3-7.
ded applications. Some applications may require large data arrays or tables that will require additional data memory. For this purpose Dynamic C supports a type of extended data memory that allows the use of additional data memory, even extending far beyond a megabyte. Requirements for stack memory depend on the type of application and particularly whether preemptive multitasking is used. If preemptive multitasking is used, then each task requires its own stack.
3.
• Input/output instructions are now accomplished by normal memory access instructions prefixed by an op code byte to indicate access to an I/O space. There are two I/O spaces, internal peripherals and external I/O devices. Some Z80 and Z180 instructions have been deleted and are not supported by the Rabbit (see Chapter 20, “Differences Rabbit vs. Z80/Z180 Instructions”). Most of the deleted instructions are obsolete or are little-used instructions that can be emulated by several Rabbit instructions.
3.3.3 Load or Store Data Using an Index Register An index register is a 16-bit register, usually IX, IY, SP or HL, that is used for the address of a byte or word to be fetched from or stored to memory. Sometimes an 8-bit offset is added to the address either as a signed or unsigned number. The 8-bit offset is a byte in the instruction word. BC and DE can serve as index registers only for the special cases below.
3.3.4 Register-to-Register Move Any of the 8-bit registers, A, B, C, D, E, H, and L, can be moved to any other 8-bit register, for example: LD A,c LD d,b LD e,l The alternate 8-bit registers can be a destination, for example: LD a’,c LD d’,b These instructions are unique to the Rabbit and require 2 bytes and four clocks because of the required prefix byte. Instructions such as LD A,d’ or LD d’,e’ are not allowed. Several 16-bit register-to-register move instructions are available.
3.3.6 Push and Pop Instructions There are instructions to push and pop the 16-bit registers AF, HL, DC, BC, IX, and IY. The registers AF', HL', DE', and BC' can be popped. Popping the alternate registers is exclusive to the Rabbit, and is not allowed on the Z80 / Z180. Examples POP HL PUSH BC PUSH IX PUSH af POP DE POP DE’ POP HL’ 3.3.7 16-bit Arithmetic and Logical Ops The HL register is the primary 16-bit accumulator. IX and IY can serve as alternate accumulators for many 16-bit operations.
The BOOL instruction is a special instruction designed to help test the HL register. BOOL sets HL to the value 1 if HL is non zero, otherwise, if HL is zero its value is not changed. The flags are set according to the result. BOOL can also operate on IX and IY.
The SBC instruction can also be used to perform a sign extension. ; extend sign of l to HL LD A,l rla SBC A,a LD h,a ; sign to carry ; a is all 1’s if sign negative ; sign extended The multiply instruction performs a signed multiply that generates a 32-bit signed result. MUL ; signed multiply of BC and DE, ; result in HL:BC - 1 byte, 12 clocks If a 16-bit by 16-bit multiply with a 16-bit result is performed, then only the low part of the 32-bit result (BC) is used.
3.3.8 Input/Output Instructions The Rabbit uses an entirely different scheme for accessing input/output devices. Any memory access instruction may be prefixed by one of two prefixes, one for internal I/O space and one for external I/O space. When so prefixed, the memory instruction is turned into an I/O instruction that accesses that I/O space at the I/O address specified by the 16bit memory address used.
3.4 How to Do It in Assembly Language—Tips and Tricks 3.4.1 Zero HL in 4 Clocks BOOL HL RR HL ; 2 clocks, clears carry, HL is 1 or 0 ; 2 clocks, 4 total - get rid of possible 1 This sequence requires four clocks compared to six clocks for LD HL,0. 3.4.
3.4.4 Comparisons of Integers Unsigned integers may be compared by testing the zero and carry flags after a subtract operation. The zero flag is set if the numbers are equal. With the SBC instruction the carry cleared is set if the number subtracted is less than or equal to the number it is subtracted from. 8-bit unsigned integers span the range 0–255. 16-bit unsigned integers span the range 0–65535.
Some simplifications are possible if one of the unsigned numbers being compared is a constant. Note that the carry has a reverse sense from SBC. In the following examples, the pseudo-code in the form LD DE,(65535-B) does not indicate a load of DE with the address pointed to by 65535-B, but simply indicates the difference between 65535 and the 16-bit unsigned integer B.
A>B A=B A<=B (!S & !V & !Z) v (S & V) (S & !V) v (!S & V & !Z) Another method of doing signed compare is to first map the signed integers onto unsigned integers by inverting bit 15. This is shown in Figure 3-8. Once the mapping has been performed by inverting bit 15 on both numbers, the comparisions can be done as if the numbers were unsigned integers. This avoids having to construct a jump tree to test the overflow and sign flags. An example is shown below.
3.5 Interrupt Structure When an interrupt occurs on the Rabbit, the return address is pushed on the stack, and control is transferred to the address of the interrupt service routine. The address of the interrupt service routine has two parts: the upper byte of the address comes from a special register and the lower byte is fixed by hardware for each interrupt, as shown in Table 6-1.
the same priority, this introduces interrupt latency while the next routine is waiting for the previous routine to allow more interrupts to take place. If a number of devices have interrupt service routines, and all interrupts are of the same priority, then pending interrupts can not take place until at least the interrupt service routine in progress is finished, or at least until it changes the interrupt priority.
3.5.2 Multiple External Interrupting Devices The Rabbit 3000 has two distinct external interrupt request lines. If there are more than two external causes of interrupts, then these lines must be shared between multiple devices. The interrupt line is edge-sensitive, meaning that it requests an interrupt only when a rising or falling edge, whichever is specified in the setup registers, takes place.
The privileged instructions to manipulate the IP register are listed below. IPSET 0 IPSET 1 IPSET 2 IPSET 3 IPRES RETI POP IP ; shift IP left and set priority 00 in bits 1,0 ; rotate IP right 2 bits, restoring previous priority ; pops IP from stack and then pops return address ; pop IP register from stack 3.5.4 Critical Sections Certain library routines may need to disable interrupts during a critical section of code.
3.5.6 Computed Long Calls and Jumps The instruction to set the XPC is privileged to so that a computed long call or jump can be made. This would be done by the following sequence. LD xpc,a JP (HL) In this case, A has the new XPC, and HL has the new PC. This code should normally be executed in the root segment so as not to pull the memory out from under the JP (HL) instruction. A call to a computed address can be performed by the following code.
4. RABBIT CAPABILITIES This chapter describes the various capabilities of the Rabbit that may not be obvious from the technical description. 4.1 Precisely Timed Output Pulses The Rabbit can output precise pulses under software control. The effect of interrupt latency is avoided because the interrupt always prepares a future pulse edge that is clocked into the output registers on the next clock. This is shown in Figure 4-1.
Pulse width modulated outputs—The minimum pulse width is 10 µs. If the repetition rate is 10 ms, then a new pulse with 1000 different widths can be generated at the rate of 100 times per second. Asynchronous communications serial output—Asynchronous output data can be generated with a new pulse every 10 µs. This corresponds to a baud rate of 100,000 bps.
4.2 Open-Drain Outputs Used for Key Scan The Parallel Port D outputs can be individually programmed to be open drain. This is useful for scanning a switch matrix, as shown in Figure 4-2. A row is driven low, then the columns are scanned for a low input line, which indicates a key is closed. This is repeated for each row.
4.3 Cold Boot Most microprocessors start executing at a fixed address, often address zero, after a reset or power-on condition. The Rabbit has two mode pins (SMODE0, SMODE1—see Figure 51). The logic state of these two pins determines the startup procedure after a reset. If both pins are grounded, then the Rabbit starts executing instructions at address zero. On reset, address zero is defined to be the start of the memory connected to the memory control lines /CS0, and /OE0.
4.4 The Slave Port The slave port allows a Rabbit to act as a slave to another processor, which can also be a Rabbit. The slave has to have only a processor chip, a RAM chip, and clock and reset signals that can be supplied by the master. The master can cold boot and download a program to the slave. The master does not have to be a Rabbit processor, but can be any type of processor capable of reading and writing standard registers. For a detailed description, see Chapter 13, “Rabbit Slave Port.
Of the three registers seen by each side for each direction of communication, the first register, slave register zero, has a special function because an interrupt can only be generated by a write to this register, which then causes an interrupt to take place on the other side of the link if the interrupt is enabled. One type of protocol is to store data first in registers 1 and 2, and then as the last step store to register 0.
5.
56 PD0 RXF, PG3 TXF, PG2 RCLKF, PG1 TCLKF, PG0 VSSIO ARXA, PD7 ATXA, PD6 ARXB, PD5 ATXB, PD4 PD3 PD2 PD1 95 3 94 4 93 5 92 6 91 7 90 8 89 9 88 10 87 11 86 12 85 13 84 14 83 15 82 16 81 17 80 18 79 19 78 20 77 21 76 A2 A3 VDDCORE VSSCORE 22 75 23 74 24 73 25 72 /SCS, I7, PE7 I6, PE6 INT1B, I5, PE5 26 71 27 70 28 69 INT0B, I4, PE4 I3, PE3 I2, PE2 29 68 30 67 31 66 VSSIO 32 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40
5.1.2 Mechanical Dimensions and Land Pattern Figure 5-2 shows the mechanical dimensions of the Rabbit 3000 LQFP package. 16.00 ± 0.25 mm 14.00 ± 0.10 mm 96 32 65 14.00 ± 0.10 mm 1 16.00 ± 0.25 mm 97 128 64 33 0.18 ± 0.05 mm 0.40 mm 1.40 ± 0.05 mm 0.10 ± 0.05 mm The same pin dimensions apply along the x axis and the y axis. 0.60 + 0.10 mm 0.15 mm 1.00 mm Figure 5-2.
Figure 5-3 shows the PC board land pattern for the Rabbit 3000 chip in a 128-pin LQFP package. This land pattern is based on the IPC-SM-782 standard developed by the Surface Mount Land Patterns Committee and specified in Surface Mount Design and Land Pattern Standard, IPC, Northbrook, IL, 1999. 16.85 mm (max.) 0.40 mm 16.85 mm (max.) 13.75 mm (min.) 12.4 mm 15.3 mm 13.75 mm (min.) 0.28 mm (max.) 1.55 mm 12.4 mm 15.3 mm TOLERANCE AND SOLDER JOINT ANALYSIS JT: 0.290.55 mm JH: 0.290.
5.2 Ball Grid Array Package 5.2.1 Pinout Rabbit 3000 (AT56C55-IZ1T, IZ2T) 128-pin Thin Map Ball Grid Array (TFBGA) 10 × 10 Body, 0.
5.2.2 Mechanical Dimensions and Land Pattern Table 5-2. Ball and Land Size Dimensions Nominal Ball Diameter (mm) Tolerance Variation (mm) Ball Pitch (mm) Nominal Land Diameter (mm) Land Variation (mm) 0.3 0.35–0.25 0.8 0.25 0.25–0.20 The design considerations in Table 5-3 are based on 5 mil design rules and assume a single conductor between solder lands. Table 5-3. Design Considerations (all dimensions in mm) Key Feature Recommendation A Solder Land Diameter 0.254 (0.
TOP VIEW 1 2 3 4 5 6 7 8 BOTTOM VIEW 9 12 11 10 10 11 12 9 8 7 6 5 4 3 2 1 A B B 0.80 A C C D E E 10.00 ± 0.05 D F G H F G H J J K K L L M M 0.80 Ball Pitch: 0.80 mm Ball Diameter: 0.3 mm (0.25~0.35) 0.20~0.30 1.20 (max.) 10.00 ± 0.05 Figure 5-5.
5.3 Rabbit Pin Descriptions Table 5-1 lists all the pins on the device, along with their direction, function, and pin number on the package. Table 5-1.
Table 5-1.
5.4 Bus Timing The external bus has essentially the same timing for memory cycles or I/O cycles. A memory cycle begins with the chip select and the address lines. One clock later, the output enable is asserted for a read. The output data and the write enable are asserted for a write. T1 Tw T2 Address (20 for memory, 16 for I/O) /IOCSn or /CSn /OEn or /IORD and /BUFEN (/BUFEN rd or wr) Data for read valid Data for write 3-s drive starts at end of T1 /WEn or /IOWR Notes: Read may have no wait states.
5.5 Description of Pins with Alternate Functions Table 5-2.
Table 5-2.
The alternate output functions identified in Table 5-2 are configured by setting the appropriate bits in the Paralle Port x Function Register. Table 5-3. Parallel Port x Alternate Functions Parallel Port x Function Register Bit(s) (PCFR) (PDFR) (PEFR) (PFFR) (PGFR) Value (Address = 0x0055) (Address = 0x0065) (Address = 0x0075) (Address = 0x003D) (Address = 0x004D) Description 0 The corresponding port bit functions normally. 1 The corresponding port bit carries its alternate signal as an output.
5.6 DC Characteristics Table 5-5. Rabbit 3000 Absolute Maximum Ratings Symbol Parameter Maximum Rating TA Operating Temperature -55° to +85°C TS Storage Temperature -65° to +150°C Maximum Input Voltage: • Oscillator Buffer Input • 5-V-tolerant I/O VDD Maximum Operating Voltage VDD + 0.5 V 5.5 V 3.6 V Stresses beyond those listed in Table 5-5 may cause permanent damage.
5.7 I/O Buffer Sourcing and Sinking Limit Unless otherwise specified, the Rabbit I/O buffers are capable of sourcing and sinking 6.8 mA of current per pin at full AC switching speeds. The limits are related to the maximum sustained current permitted by the metallization on the die.
70 Rabbit 3000 Microprocessor
6.
Table 6-1.
6.1 Default Values for all the Peripheral Control Registers The default values for all of the peripheral control registers are shown in Table 6-2. The registers within the CPU affected by reset are the Stack Pointer (SP), the Program Counter (PC), the IIR register, the EIR register, and the IP register. The IP register is set to all ones (disabling all interrupts), while all of the other listed CPU registers are reset to all zeros. Table 6-2.
Table 6-2.
Table 6-2.
Table 6-2.
Table 6-2.
Table 6-2.
7. MISCELLANEOUS FUNCTIONS 7.1 Processor Identification Four read-only registers are provided to allow software to identify the Rabbit microprocessor and recognize the features and capabilities of the chip. Five bits in each of these registers are unique to each version of the chip.
Table 7-3. Global CPU Register Global CPU Register (GCPU) Bit(s) Value 7 0 Program fetch as a function of the SMODE pins. (read only) 1 Ignore the SMODE pins program fetch function. 6:5 read 4:0 00001 (Address = 0x2E) Description These bits report the state of the SMODE pins. CPU identifier for this version of the chip. Table 7-4. Global Revision Register Global Revision Register (GREV) Bit(s) Value 7 0 Program fetch as a function of the SMODE pins.
32.768 kHz Clock The 32.768 kHz clock is primarily used to clock the on-chip real-time clock. In addition, it is also used to support remote cold boot via Serial Port A, driving the 2400 baud communications used to initiate the cold boot. Another function of the 32.768 kHz oscillator is to drive the low power sleepy mode with the main oscillator shut down to reduce power. The 32.768 kHz clock can be left out of a system provided that its functions are not required.
Table 7-5. Global Control/Status Register Global Control/Status Register Bit(s) 7:6 (rd-only) (GCSR) Value (Address = 0x00) Description 00 No Reset or Watchdog Timer time-out since the last read. 01 The Watchdog Timer timed out. These bits are cleared by a read of this register. 10 This bit combination is not possible. 11 Reset occurred. These bits are cleared by a read of this register. 0 No effect on the Periodic interrupt. This bit will always be read as zero.
7.3 Clock Doubler The clock doubler is provided to allow a lower frequency crystal to be used for the main oscillator and to provide an added range of clock frequency adjustability. The clock doubler is controlled via the Global Clock Double Register as shown in Table 7-7. Table 7-7. Global Clock Double Register Global Clock Double Register (GCDR) Bit(s) Value 7:4 xxxx Reserved 0000 The clock doubler circuit is disabled.
When the clock doubler is used and there is no subsequent division of the clock, the output clock will be asymmetric, as shown in Figure 7-2. P Oscillator 48% 52% Oscillator delayed and inverted Doubled clock Delay time 0.48P Example Write Cycle 0.52P 0.48P 0.52P Address / CS Data out write pulse early write pulse option Address / CS Example Read Cycle data out from mem output enb early output enb option Figure 7-2.
variation in period on alternate clocks. This does not affect the no-wait states memory access time since two adjacent clocks are always used. However, the maximum allowed clock speed must be slightly reduced if the clock is supplied via the clock doubler. The only signals clocked on the falling edge of the clock are the memory and I/O write pulses and the early option memory output enable. See Chapter 8 for more information on the early output enable and write enable options.
7.4 Clock Spectrum Spreader When enabled the spectrum spreader stretches and compresses the clocks in a complex pattern that results in spreading the energy in the clock harmonics over a wide range of frequencies. The spectrum spreader has a normal and a strong setting. With either setting the peak spectral strength of the clock harmonics is reduced by approximately 15 dB for frequencies above 100 MHz.
7.5 Chip Select Options for Low Power Some types of flash memory and RAM consume power whenever the chip select is enabled even if no signals are changing. The chip select behavior of the Rabbit 3000 can be modified to reduce unnecessary power consumption when the Rabbit 3000 is running at a reduced clock speed. The short chip select option can be enabled when the processor clock is divided (by 4, 6, or 8) so as to run at a lower speed.
When operating in the 32 kHz mode, it is also possible to further divide the clock to a frequency as low as 2 kHz, further reducing execution speed and current consumption. Global Power Save Control Register Bit(s) 7:5 4 3 2:0 Value (GPSCR) (Address = 0x0D) Description 000 Self-timed chip selects are disabled. 001 This bit combination is reserved and should not be used. 01x This bit combination is reserved and should not be used.
T1 T2 clock ADDR Valid DATA MEMCSxB MEMOExB Figure 7-4. Short Chip Select Memory Read T1 T2 32 kHz ADDR DATA Valid Valid MEMCSxB MEMOExB ~100 ns Figure 7-5.
7.6 Output Pins CLK, STATUS, /WDTOUT, /BUFEN Certain output pins can have alternate assignments as specified in Table 7-9. Table 7-9. Global Output Control Register (GOCR = 0x0E) Bit(s) Value Description 00 CLK pin is driven with peripheral clock. 01 CLK pin is driven with peripheral clock divided by 2. 10 CLK pin is low. 11 CLK pin is high. 00 STATUS pin is active (low) during a first opcode byte fetch. 01 STATUS pin is active (low) during an interrupt acknowledge. 10 STATUS pin is low.
7.7 Time/Date Clock (Real-Time Clock) The time/date clock (RTC) is a 48-bit (ripple) counter that is driven by the 32.768 kHz oscillator. The RTC is a modified ripple counter composed of six separate 8-bit counters. The carries are fed into all six 8-bit counters at the same time and then ripple for 8 bits. The time for this ripple to take place is a few nanoseconds per bit, and certainly should not should not exceed 200 ns for all 8 bits, even when operating at low voltage.
Table 7-10. Real-Time Clock RTCxR Data Registers Real-Time Clock x Holding Register Bit(s) 7:0 Value (RTC0R) R/W (RTC1R) (RTC2R) (RTC3R) (RTC4R) (RTC5R) (Address = 0x02) (Address = 0x03) (Address = 0x04) (Address = 0x05) (Address = 0x06) (Address = 0x07) Description Read The current value of the 48-bit RTC holding register is returned. Write Writing to the RTC0R transfers the current count of the RTC to six holding registers while the RTC continues counting. Table 7-11.
7.8 Watchdog Timer The watchdog timer is a 17-bit counter. In normal operation it is driven by the 32.768 kHz clock. When the watchdog timer reaches any of several values corresponding to a delay of from 0.25 to 2 seconds, it “times out.” When it times out, it emits a 1-clock pulse from the watchdog output pin and it resets the processor via an internal circuit. To prevent this timeout, the program must “hit” the watchdog timer before it times out. The hit is accomplished by storing a code in WDTCR.
Table 7-13. Watchdog Timer Test Register (WDTTR adr = 0x09) Bit(s) Value Description 0x51 Clock the least significant byte of the watchdog timer from the peripheral clock. (Intended for chip test and code 0x54 below only.) 0x52 Clock the most significant byte of the watchdog timer from the peripheral clock. (Intended for chip test and code 0x54 below only.) 0x53 Clock both bytes of the watchdog timer, in parallel, from the peripheral clock. (Intended for chip test and code 0x54 below only.
7.9 System Reset The Rabbit 3000 contains a master reset input (pin 46), which initializes everything in the device except for the Real-Time Clock (RTC). This reset is delayed until the completion of any write cycles in progress to prevent potential corruption of memory. If no write cycles are in progress the reset takes effect immediately. The reset sequence requires a minimum of 128 cycles of the fast oscillator to complete, even if no write cycles were in progress at the start of the reset.
Table 7-14.
7.10 Rabbit Interrupt Structure An interrupt causes a call to be executed, pushing the PC on the stack and starting to execute code at the interrupt vector address. The interrupt vector addresses have a fixed lower byte value for all interrupts. The upper byte is adjustable by setting the registers EIR and IIR for external and internal interrupts respectively. There are only two external interrupts generated by transitions on certain pins in Parallel Port E. The interrupt vectors are shown in Table 6-2.
Table 7-15. Interrupts—Priority and Action to Clear Requests Priority Highest Lowest Interrupt Source Action Required to Clear the Interrupt External 1 Automatically cleared by the interrupt acknowledge. External 0 Automatically cleared by the interrupt acknowledge. Periodic (2 kHz) Read the status from the GCSR. Quadrature Decoder Read the status from the QDCSR. Timer B Read the status from the TBSR. Timer A Read the status from the TASR. Input Capture Read the status from the ICCSR.
7.10.1 External Interrupts There are two external interrupts. Each interrupt has 2 input pins that can be used to trigger the interrupt. The inputs have a pulse catcher that can detect rising, falling or either rising or falling edges. INT1A [PE1] pulse catcher INT1B [PE5] pulse catcher #1 interrupt acknowledge INT0A [PE0] pulse catcher INT0B [PE4] pulse catcher #0 interrupt acknowledge Figure 7-6.
Table 7-16. Control Registers for External Interrupts Reg Name Reg Address Bits 7,6 Bits 5,4 Bits 3,2 Bits 1,0 I0CR 10011000 xx INT0B PE4 INT0A PE0 Enb INT0 I1CR 10011001 xx INT1B PE5 INT1A PE1 Enb INT1 edge triggered 00-disabled 10-rising 01-falling 11-both edge triggered 00-disabled 10-rising 01-falling 11-both interrupt 00-disable 01-pri 1 10-pri 2 11-pri 3 7.10.
7.11 Bootstrap Operation The device provides the option of bootstrap from any of three sources: from the Slave Port, from Serial Port A in clocked serial mode, or from Serial Port A in asynchronous mode. This is controlled by the state of the SMODE pins after reset. Bootstrap operation is disabled if (SMODE1, SMODE0) = (0, 0). Bootstrap operation inhibits the normal fetch of code from memory, and instead substitutes the output of a small internal boot ROM for program fetches.
Serial Port A is selected for bootstrap operation as a clocked serial port when SMODE = 10. In this case bit 7 of Parallel Port C is used for the serial data and bit 1 of Parallel Port B is used for the serial clock. Note that the serial clock must be externally supplied for bootstrap operation. This precludes the use of a serial EEPROM for bootstrap operation. Serial Port A is selected for bootstrap operation as an asynchronous serial port when SMODE = 11.
7.12 Pulse Width Modulator The Pulse Width Modulator consists of a ten-bit free running counter, and four width registers. Each PWM output is High for "n + 1" counts out of the 1024-clock count cycle, where "n" is the value held in the width register. The PWM output High time can optionally be spread throughout the cycle to reduce ripple on the externally filtered PWM output. The PWM is clocked by the output of Timer A9.
n=255, normal (256 counts) n=255, spread (64 counts) (64 counts) (64 counts) (64 counts) (64 counts) (64 counts) n=256, spread (65 counts) (64 counts) n=257, spread (65 counts) (64 counts) n=258, spread (65 counts) n=259, spread (65 counts) n=259, normal (65 counts) (64 counts) (65 counts) (65 counts) (64 counts) (65 counts) (65 counts) (65 counts) (260 counts) Table 7-17.
7.13 Input Capture The two-channel Input Capture can be used to time input signals from various port pins. Each Input Capture channel consists of a sixteen-bit counter that is clocked by the output of Timer A8, and can be connected to one or two out of sixteen parallel port pins. The Input Capture channel captures the state of its counter upon either of two programmed conditions and can then generate an interrupt. The programmed conditions can also be used to start and stop the counter.
Each Input Capture counter operates in one of three modes, or can be disabled. The counter is never automatically reset, but must be reset by a software command. Although it does not generate an interrupt, there is a status bit which is set when the counter overflows (counts from 0xFFFF to 0x0000) so that software can recognize this condition.
Table 7-19. Input Capture Control/Status Register Input Capture Control/Status Register Bit(s) (ICCSR) Value 7:2 (read) (Address = 0x56) Description These status bits (but not the interrupt enable bits) are cleared by the read of this register, as is the Input Capture Interrupt. 7 0 The Input Capture 2 Start condition has not occurred. (read) 1 The Input Capture 2 Start condition has occurred. 7 0 The corresponding Input Capture 2 Start interrupt is disabled.
Table 7-20. Input Capture Control Register Input Capture Control Register Bit(s) (ICCR) Value 7:2 (Address = 0x57) Description These bits are ignored. 1:0 00 Input Capture interrupts are disabled. 01 Input Capture interrupt use Interrupt Priority 1. 10 Input Capture interrupt use Interrupt Priority 2. 11 Input Capture interrupt use Interrupt Priority 3. Table 7-21.
Table 7-22. Input Capture Source x Register Input Capture Source x Register (ICS1R) (ICS2R) Bit(s) Value 7:6 00 Parallel Port C used for Start condition input. 01 Parallel Port D used for Start condition input. 10 Parallel Port F used for Start condition input. 11 Parallel Port G used for Start condition input. 00 Use port bit 1 for Start condition input. 01 Use port bit 3 for Start condition input. 10 Use port bit 5 for Start condition input. 11 Use port bit 7 for Start condition input.
7.14 Quadrature Decoder The two-channel Quadrature Decoder accepts inputs, via Port F, from two external optical incremental encoder modules. Each channel of the Quadrature Decoder accepts an inphase (I) and a quadrature-phase (Q) signal and provides 8-bit counters to track shaft rotation and provide interrupts when the count goes from 0x00 to 0xFF or from 0xFF to 0x00. The Quadrature Decoder contains digital filters on the inputs to prevent false counts.
Peri Clock Timer A10 Rejected Accepted The Quadrature Decoder generates an interrupt when the counter increments from 0xFF to 0x00 or when the counter decrements from 0x00 to 0xFF. The timing for the interrupt is shown below. Note that the status bits in the QDCSR are set coincident with the interrupt, and the interrupt (and status bits) are cleared by reading the QDCSR.
Table 7-25. Quadrature Decoder Control/Status Register Quad Decode Control/Status Register (QDCSR) (Address = 0x90) Bit(s) Value 7 0 Quadrature Decoder 2 did not increment from 0xFF. (read-only) 1 Quadrature Decoder 2 incremented from 0xFF to 0x00. This bit is cleared by a read of his register. 6 0 Quadrature Decoder 2 did not decrement from 0x00. (read-only) 1 Quadrature Decoder 2 decremented from 0x00 to 0xFF. This bit is cleared by a read of this register.
Table 7-26. Quadrature Decoder Control Register Quad Decode Control Register Bit(s) 7:6 (QDCR) (Address = 0x91) Value Description 00 Disable Quadrature Decoder 2 inputs. Writing a new value to these bits will not cause Quadrature Decoder 2 to increment or decrement. 01 This bit combination is reserved and should not be used. 10 Quadrature Decoder 2 inputs from Port F bits 3 and 2. 11 Quadrature Decoder 2 inputs from Port F bits 7 and 6. 5:4 These bits are ignored.
114 Rabbit 3000 Microprocessor
8. MEMORY INTERFACE AND MAPPING 8.1 Interface for Static Memory Chips Static memory chips generally have address lines, data line, a chip select line, an output enable line and a write enable. The Rabbit 3000 has these same lines that can connect directly to a number of static memory chips. The chip selects are not completely interchangeable because certain chip selects have special functions.
DATA LINES (8) Rabbit 3000 ADDRESS LINES (20) STATIC MEMORY FLASH /CS /CS0 /CS1 /CS2 /OE /WE /OE0 /OE1 /WE0 /WE1 STATIC MEMORY RAM /CS /OE /WE Figure 8-2.
8.2 Memory Mapping Overview See Section 3.2, “Memory Mapping,” for a discussion of Rabbit memory mapping. Figure 8-3 shows an overview of the Rabbit memory mapping. The task of the memory mapping unit is to accept 16-bit addresses and translate them to 20-bit addresses. The memory interface unit accepts the 20-bit addresses and generates control signals applied directly to the memory chips. Processor Memory Mapping Unit Memory Interface Unit Memory Chips Figure 8-3.
64K Extended code XPC segment (8K) Boundary SEGSIZE[4..7] Stack segment (4K typ) Boundary SEGSIZE[0..3] Data segment XPC STACKSEG DATASEG 00 + Root segment 0K 16-bit address 20-bit address Figure 8-4. Memory Segments The memory management unit accepts a 16-bit address from the processor and translates it into a 20-bit address. The procedure to do this works as follows. 1. It is determined which segment the 16-bit address belongs to by inspecting the upper 4 bits of the address.
8.4 Memory Interface Unit The 20-bit memory addresses generated by the memory-mapping unit feed into the memory interface unit. The memory interface unit has a separate write-only control register for each 256K quadrant of the 1M physical memory. This control register specifies how memory access requests to that quadrant are to be dispatched to the memory chips connected to the Rabbit.
8.5 Memory Bank Control Registers Table 8-3 describes the operation of the four memory bank control registers. The registers are write-only. Each register controls one quadrant in the 1M address space. Table 8-3. Memory Bank Control Register x (MBxCR = 0x014 + x) Memory Bank x Control Register Bit(s) Value (MB0CR) (MB1CR) (MB2CR) (MB3CR) (Address = 0x014) (Address = 0x015) (Address = 0x016) (Address = 0x017) Description 00 Four wait states for accesses in this bank.
Bit 3—Inhibits the write pulse to memory accessed in this quadrant. Useful for protecting flash memory from an inadvertent write pulse, which will not actually write to the flash because it is protected by lock codes, but will temporarily disable the flash memory and crash the system if the memory is used for code. Bit 2—Selects which set of the two lines /OEx and /WEx will be driven for memory accesses in this quadrant.
Table 8-5. MMU Expanded Code Register (MECR = 0x018) MMU Expanded Code Register Bit(s) Value 7:3 2:0 (MECR) (Address = 0x018) Description These bits are ignored for write, and return zeros when read. 0xx Normal operation. 100 For an XPC access, use MB0CR independent of A19-A18. 101 For an XPC access, use MB1CR independent of A19-A18. 110 For an XPC access, use MB2CR independent of A19-A18. 111 For an XPC access, use MB3CR independent of A19-A18.
The Breakpoint/Debug controller allows the RST 28 instruction to be used as a software breakpoint. Normally the RST 28 instruction causes a call to a particular location in memory, but the operation of this instruction is modified when the breakpoint/debug feature is enabled. The RST 28 instruction is treated as a NOP in the breakpoint/debug mode. Table 8-7. Breakpoint/Debug Control Register (BDCR, adr = 0x01C ) Breakpoint/Debug Control Register Bit(s) Value 7 0 Normal RST 28 operation.
8.7 Instruction and Data Space Support Instruction and Data space (I and D space) support is accomplished by optionally inverting address lines A16 and/or A19 when the processor accesses D space, but not inverting those lines when the processor accesses I space. The MMIDR register (see Table 8-8) is used to control this inversion.
are mapped into contiguous regions of memory to create a continuous root code segment starting at the bottom of physical memory in flash. In the I space the division between the root segment and the data segment is irrelevant because the DATASEG register contains zero and the division between the segments defined by the lower 4 bits of the SEGSIZE register does not mark a division in physical memory for code space.
64k 0k 52k 64k+4*n alloc xcode 512k+4*n xconsts 512k 512k+52k 1024k alloc xdata vars Root I Space allocate vars alloc consts Constant D Space Flash memory available for extended code, constant data. Variable D Space Ram memory available. Figure 8-6. Use of Physical Memory Separate I & D Space Model In Figure 8-6 arrows indicate the direction in which variables and constants are allocated as the compile or assemble proceeds. Each of these arrows starts at a constant location in physical memory.
8.8 How the Compiler Compiles to Memory The compiler actually generates code for root code and constants and extended code and extended constants. It allocates space for data variables, but does not generate data bits to be stored in memory. In any but the smallest programs, most of the code is compiled to extended memory. This code executes in the 8K window from E000 to FFFF. This 8K window uses paged access.
128 Rabbit 3000 Microprocessor
9. PARALLEL PORTS The Rabbit has seven 8-bit parallel ports designated A, B, C, D, E, F, and G. The pins used for the parallel ports are also shared with numerous other functions as shown in Table 5-2. The important properties of the ports are summarized below. • Port A—Shared with the slave port data interface and auxiliary I/O data bus. • Port B—Shared with control lines for slave port, auxiliary I/O address bus, and clock I/O for clocked serial mode option for Serial Ports A and B.
9.1 Parallel Port A Parallel Port A has a single read/write register: Table 9-1. Parallel Port A Registers Register Name Mnemonic I/O address R/W Reset Port A Data Register PADR 0x30 R/W xxxxxxxx Slave Port Control Register SPCR 0x24 R/W 0xx00000 Table 9-2. Parallel Port A Data Register Bit Functions Bit 7 PADR (R/W) adr = 0x030 PA7 Bit 6 PA6 Bit 5 PA5 Bit 4 PA4 Bit 3 PA3 Bit 2 PA2 Bit 1 PA1 Bit 0 PA0 This register should not be used if the slave port or auxiliary I/O bus is enabled.
9.2 Parallel Port B Parallel Port B, has eight pins that can programmed individually to be inputs and outputs. After reset, Parallel Port B comes up as six inputs (PB[5:0]) and two outputs (PB7 and PB6). The output value on pins PB6 and PB7 (package pins 99, 100) will be low. Table 9-3. Parallel Port B Registers Register Name Mnemonic I/O address R/W Reset Port B Data Register PBDR 0x40 R/W 00xxxxxx Port B Data Direction Register PBDDR 0x47 W 11000000 Table 9-4.
9.3 Parallel Port C Parallel Port C, shown in Table 9-6, has four inputs and four outputs. The even-numbered ports, PC0, PC2, PC4, and PC6, are outputs. The odd-numbered ports, PC1, PC3, PC5, and PC7, are inputs. When the data register is read, bits 1,3,5,7 return the value of the voltage on the pin. Bits 0,2,4,6 return the value of the signal driving the output buffers. The signal driving the output buffers and the value of the output pin are normally the same.
9.4 Parallel Port D Parallel Port D, shown in Figure 9-1, has eight pins that can be programmed individually to be inputs or outputs. When programmed as outputs, the pins can be individually selected to be open-drain outputs or standard outputs. Port D pins can be addressed by bit if desired. The output registers are cascaded and timer-controlled, making it possible to generate precise timing pulses.
ARXA PD7 PD6 ATXA ARXB PD5 PD4 ATXB inputs I/O Data perclk/2 Timer A1 Timer B1 Timer B2 Driver—optional open drain PD3 PD0 perclk/2 Timer A1 Timer B1 Timer B2 Figure 9-1.
Table 9-8.
The following registers are described in Table 9-8 and in Table 9-9. • PDDR—Parallel Port D data register. Read/Write. • PDDDR—Parallel Port D data direction register. A "1" makes the corresponding pin an output. Write only. • PDDCR—Parallel Port D drive control register. A "0" makes the corresponding pin a regular output. A "1" makes the corresponding pin an open-drain output. Write only. • PDFR—Parallel Port D function control register.
9.5 Parallel Port E Parallel Port E, shown in Figure 9-2, has eight I/O pins that can be individually programmed as inputs or outputs. PE7 is used as the slave port chip select when the slave port is enabled. Each of the port E outputs can be configured as an I/O strobe. In addition, four of the port E lines can be used as interrupt request inputs. The output registers are cascaded and timer-controlled, making it possible to generate precise timing pulses.
Table 9-10.
Table 9-11.
9.6 Parallel Port F Parallel Port F is a byte-wide port with each bit programmable for data direction and drive. These are simple inputs and outputs controlled and reported in the Port F Data Register. As outputs, the bits of the port are buffered, with the data written to the Port F Data Register transferred to the output pins on a selected timing edge.
Table 9-15. Parallel Port F Control Register (adr = 0x03C) Bits 7, 6 x,x Bits 5, 4 Bits 3, 2 00—clock upper nibble on pclk/2 01—clock on timer A1 x,x 10—clock on timer B1 11—clock on timer B2 Bits 1, 0 00—clock lower nibble on pclk/2 01—clock on timer A1 10—clock on timer B1 11—clock on timer B2 The following registers are described in Table 9-14 and in Table 9-15. • PFDR—Port F data register. Reads value at pins. Writes to port F preload register. • PFCR—Parallel Port F control register.
The functionality of the Parallel Port F pins is not affected for pulse width modulation outputs and serial clock outputs, except that the Parallel Port F function and direction registers should be set up before a conflicting function on Parallel Port A is in use, since writing to these registers also writes to the Parallel Port A output register. 9.6.1.
9.7 Parallel Port G Parallel Port G is a byte-wide port with each bit programmable for data direction and drive. These are simple inputs and outputs controlled and reported in the Port G Data Register. As outputs, the bits of the port are buffered, with the data written to the Port G Data Register transferred to the output pins on a selected timing edge.
Table 9-18. Parallel Port G Control Register (adr= 0x04C) Bits 7, 6 x,x Bits 5, 4 Bits 3, 2 00—clock upper nibble on pclk/2 01—clock on timer A1 x,x 10—clock on timer B1 11—clock on timer B2 Bits 1, 0 00—clock lower nibble on pclk/2 01—clock on timer A1 10—clock on timer B1 11—clock on timer B2 The following registers are described in Table 9-17 and in Table 9-18. • PGDR—Port G data register. Reads value at pins. Writes to port G preload register. • PGCR—Parallel Port G control register.
10. I/O BANK CONTROL REGISTERS The pins of Port E can be set individually to be I/O strobes. Each of the eight possible I/O strobes has a control register that controls the nature of the strobe and the number of wait states that will be inserted in the I/O bus cycle. Writes can also be suppressed for any of the strobes. The types of strobes are shown in Figure 10-1. Each of the eight I/O strobes is active for addresses occupying 1/8th of the 64K external I/O address space.
Table 10-1 shows how the eight I/O bank control registers are organized. Table 10-1. I/O Bank x Control Register I/O Bank x Control Register (IB0CR) (IB1CR) (IB2CR) (IB3CR) (IB4CR) (IB5CR) (IB6CR) (IB7CR) (Address = 0x0080) (Address = 0x0081) (Address = 0x0082) (Address = 0x0083) (Address = 0x0084) (Address = 0x0085) (Address = 0x0086) (Address = 0x0087) Bit(s) Value 7:6 00 Fifteen wait states for accesses in this bank. 01 Seven wait states for accesses in this bank.
The eight I/O bank control registers determine the number of I/O wait states applied to an external I/O access within the zone controlled by each register even if the associated strobes are not enabled. Note that the /IORD and /IOWR signals reflect these registers as well. The control over the generation of wait states is independent of whether or not the associated strobe in Port E is enabled. The upper 2 bits of each register determine the number of wait states.
148 Rabbit 3000 Microprocessor
11. TIMERS There are two timers—Timer A and Timer B. Timer A is intended mainly for generating the clock for various peripherals, baud clock for the serial ports, a periodic clock for clocking Parallel Ports D and E, or for generating periodic interrupts. Timers A1–A7 are general-purpose timers, and Timers A8–A10 are dedicated to specific peripherals. Timer B can be used for the same functions, but it cannot generate the baud clock.
11.1 Timer A Timer A consists of ten separate countdown timers A1–A10 as shown in Figure 11-1. Timers A1 and A2–A10 are 8-bit countdown registers as shown in Figure 11-2. The reload register can contain any number in the range from 0 to 255. The counter divides by (n+1). For example, if the reload register contains 127, then 128 pulses enter on the left before a pulse exits on the right.
For seven of the counters (A1–A7), the terminal count condition is reported in a status register and can be programmed to generate an interrupt. There is one interrupt vector for Timer A and a common interrupt priority. A common status register (TACSR) has a bit for each timer that indicates if the output pulse for that timer has taken place since the last read of the status register. When the status register is read, these bits are cleared. No bit will be lost.
The following table summarizes Timer A’s capabilities. Table 11-2.
Table 11-3. Timer A Control and Status Register (continued) Timer A Control and Status Register (TACSR) (Address = 0x00A0) Bit(s) Value 4 (write) 0 A4 interrupt disabled. 1 A4 interrupt enabled. 3 (read) 0 A3 counter has not reached its terminal count. 1 A3 count done. This status bit is cleared by a read of this register. 3 (write) 0 A3 interrupt disabled. 1 A3 interrupt enabled. 2 (read) 0 A2 counter has not reached its terminal count. 1 A2 count done.
The control register (TACR) is laid out as shown in Table 11-4. Table 11-4. Timer A Control Register Timer A Control Register Bit(s) Value (TACR) (Address = 0x00A4) Description 0 Timer A7 clocked by the main Timer A clock. 1 Timer A7 clocked by the output of Timer A1. 0 Timer A6 clocked by the main Timer A clock. 1 Timer A6 clocked by the output of Timer A1. 0 Timer A5 clocked by the main Timer A clock. 1 Timer A5 clocked by the output of Timer A1.
The time constant register for each timer (TATxR) is simply an 8-bit data register holding a number between 0 and 255. This time constant will take effect the next time that the Timer A counter counts down to zero. The timer counts modulo (divide-by) n+1, where n is the programmed time constant. The time constant registers are write only. The time constant registers are listed in Table 11-1. 11.1.2 Practical Use of Timer A Timer A is disabled (bit 0 in control and status register) on power-up.
11.2 Timer B Figure 11-1 shows a block diagram of Timer B. The Timer B counter can be driven directly by perclk/2, by that clock divided by 8, or by the output of Timer A1. Timer B has a continuously running 10-bit counter. The counter is compared against two match registers, the B1 match register and the B2 match register. When the counter transitions to a value equal to a match register, an internal pulse with a length of 1 peripheral clock is generated.
The control/status register for Timer B (TBCSR) is laid out as shown in Table 11-7. Table 11-7. Timer B Control and Status Register Timer B Control and Status Register Bit(s) (TBCSR) Value 7:3 (Address = 0x00B0) Description These bits are always read as zero. 2 (read) 2 (write) 1 (read) 1 (write) 0 Timer B2 comparator has not encountered a match condition. 1 Timer B2 comparator has encountered a match condition.
The MSB x registers for Timer B (TBM1R/TBM2R) are laid out as shown in Table 11-9. Table 11-9. Timer B Count MSB x Registers Timer B Count MSB x Register Bit(s) Value 7:6 Write 5:0 (TBM1R) (TBM2R) (Address = 0xB2) (Address = 0xB4) Description The two MSBs of the comparae value for the Timer B comparator are stored. This compare value will be loaded into the actual comparator when the current compare detects a match. These bits are always read as zeroes.
11.2.1 Using Timer B Normally the prescaler is set to divide perclk/2 by a number that provides a counting rate appropriate to the problem. For example, if the clock is 22.1184 MHz, then perclk/2 is 11.0592 MHz. A Timer B clock rate of 11.0592 MHz will cause a complete cycle of the 10-bit clock in 92.6 µs. Normally an interrupt will occur when either of the comparators in Timer B generates a pulse.
Timer B can be used for various purposes. The 10-bit counter can be read to record the time at which an event takes place. If the event creates an interrupt, the timer can be read in the interrupt routine. The known time of execution of the interrupt routine can be subtracted. The variable interrupt latency is then the uncertainty in the event time. This can be as little 19 clocks if the interrupt is the highest priority interrupt. If the system clock is 20 MHz, the counter can count as fast as 10 MHz.
12. RABBIT SERIAL PORTS The Rabbit 3000 has 6 on-chip serial ports designated A, B, C, D, E, and F. All the ports can perform asynchronous serial communications at high baud rates. Ports A-D can operate as clocked ports. Ports A and B can be switched to alternate pins. Ports E and F support SDLC/HDLC synchronous communications in addition to standard asynchronous communications.
Table 12-1. Serial Port Signals (continued) Serial Port Signal Name Serial Port F Function TXF Serial Transmit Out RXF Serial Transmit In TCLKF Optional external transmit clock RCLKF Optional external receive clock Figure 12-1 shows a block diagram of the serial ports.
The individual serial ports are capable of operating at baud rates in excess of 500,000 bps in the asynchronous mode, and 8 times faster than that in the synchronous mode. Either 7 or 8 data bits may be transmitted and received in the asynchronous mode. The so-called "9th" bit or address bit mode of operation is also supported. The “9th” bit can be set high or low by accessing the appropriate serial port register.
12.1 Serial Port Register Layout Figure 12-2 shows a functional block diagram of a serial port. Each serial port has a data register, a control register and a status register. Writing to the data register starts transmission. The least significant bit (LSB) is always transmitted first. This is true for both asycnchronous and synchronous communication. If the write is performed to an alternate data register address, the extra address bit or 9th bit (8th bit if 7 data bits) is sent.
The clock input to the serial port unit must be 8 or 16 (selectable) times the baud rate in the asynchronous mode and 2 times the baud rate for the clocked serial mode when the internal clock is used. Timers A2–A7 supply the input clock for Serial Ports A–F. These timers can divide the frequency by any number from 1 to 256 (see Chapter 11). The input frequency to the timers can be selected in different ways described in the documentation for the timers.
12.2 Serial Port Registers Each serial port has 6 registers shown in the tables below. The status, control and extended registers may have somewhat different formats for different serial ports. Table 12-2.
Table 12-5. Serial Port D Registers Register Name Mnemonic I/O Address R/W Reset Serial Port D Data Register SDDR 0xF0 R/W xxxxxxxx Serial Port D Address Register SDAR 0xF1 W xxxxxxxx Serial Port D Long Stop Register SDLR 0xF2 W xxxxxxxx Serial Port D Status Register SDSR 0xF3 R 0xx00000 Serial Port D Control Register SDCR 0xF4 W xx000000 Serial Port D Extended Register SDER 0xF5 W 00000000 Table 12-6.
Table 12-8. Data Register All Ports Serial Port x Data Register Bit(s) Value (SADR) (SBDR) (SCDR) (SDDR) (SEDR) (SFDR) (Address = 0xC0) (Address = 0xD0) (Address = 0xE0) (Address = 0xF0) (Address = 0xC8) (Address = 0xD8) Description Read Returns the contents of the receive buffer. Write Loads the transmit buffer with a data byte for transmission. 7:0 Table 12-9.
Table 12-10. Long Stop Register All Ports Serial Port x Long Stop Register Bit(s) Value (Address = 0xC2) (Address = 0xD2) (Address = 0xE2) (Address = 0xF2) (Address = 0xCA) (Address = 0xDA) Description Read Returns the contents of the receive buffer. Write Loads the transmit buffer with an address byte, marked with a “one” address bit, for transmission. In HDLC mode the last byte of a frame is written to this register to enable subsequent closing Flag transmission.
Table 12-11. Status Register Asynchronous Mode Only (All Ports) Serial Port x Status Register Bit(s) Value 1 There is a byte in the receive buffer. The transition from "0" to "1" sets the receiver interrupt request flip-flop. The interrupt FF is cleared when the character is read from the data buffer. The interrupt FF will be immediately set again if there are more characters available in the FIFO or shift register to be transferred into the data buffer.
Table 12-12. Status Register Clocked Serial (Ports A-D only) Serial Port x Status Register Bit(s) Value (Address = (Address = (Address = (Address = 0xC3) 0xD3) 0xE3) 0xF3) Description (Clocked serial mode only) 0 The receive data register is empty 1 There is a byte in the receive buffer. The serial port will request an interrupt while this bit is set. The interrupt is cleared when the receive buffer is empty. 0 This bit is always zero in clocked serial mode.
Table 12-13. Status Register HDLC Mode (Ports E and F only) Serial Port x Status Register Bit(s) Value (SESR) (SFSR) (Address = 0xCB) (Address = 0xD3) Description (HDLC mode only) 0 The receive data register is empty 1 There is a byte in the receive buffer. The serial port will request an interrupt while this bit is set. The interrupt is cleared when the receive buffer is empty. 00 The byte in the receive buffer is data. 01 The byte in the receive buffer was followed by an Abort.
Table 12-14. Serial Port Control Register Ports A and B Serial Port x Control Register (SACR) (SBCR) (Address = 0xC4) (Address = 0xD4) Bit(s) Value 7:6 00 No operation. These bits are ignored in the Async mode. 01 In clocked serial mode, start a byte receive operation. 10 In clocked serial mode, start a byte transmit operation. 11 In clocked serial mode, start a byte transmit operation and a byte receive operation simultaneously. 00 Parallel Port C is used for input.
Table 12-15. Serial Port Control Register Ports C and D Serial Port x Control Register Bit(s) 7:6 Value (SCCR) (SDCR) (Address = 0xE4) (Address = 0xF4) Description 00 No operation. These bits are ignored in the async mode. 01 In clocked serial mode, start a byte receive operation. 10 In clocked serial mode, start a byte transmit operation. 11 In clocked serial mode, start a byte transmit operation and a byte receive operation simultaneously. 0 Enable the receiver input.
Table 12-16. Serial Port Control Register Ports E and F Serial Port x Control Register Bit(s) Value (SECR) (SFCR) (Address = 0xCC) (Address = 0xDC) Description 00 No operation. These bits are ignored in the Async mode. 01 In HDLC mode, force receiver in Flag Search mode. 10 No operation. 11 In HDLC mode, transmit an Abort pattern. 0 Enable the receiver input. 1 Disable the receiver input. x This bit is ignored. 00 Async mode with 8 bits per character.
Table 12-17. Extended Register Asynchronous Mode All Ports Serial Port x Extended Register Bit(s) Value 7:5 xxx (SAER) (SBER) (SCER) (SDER) (SEER) (SFER) (Address = 0xC5) (Address = 0xD5) (Address = 0xE5) (Address = 0xF5) (Address = 0xCD) (Address = 0xDD) Description (Async mode only) These bits are ignored in async mode. 0 Normal async data encoding. 1 Enable RZI coding (3/16ths bit cell IrDA-compliant). 0 Normal Break operation. This option should be selected when address bits are expected.
Table 12-18. Extended Register Clocked Serial Mode (Ports A-D only) Serial Port x Extended Register Bit(s) Value (SAER) (SBER) (SCER) (SDER) (Address = 0xC5) (Address = 0xD5) (Address = 0xE5) (Address = 0xF5) Description (Clocked serial mode only) 0 Normal clocked serial operation. 1 Timer synchronized clocked serial operation. 0 Timer-synchronized clocked serial uses Timer B1. 1 Timer-synchronized clocked serial uses Timer B2. 00 Normal clocked serial clock polarity, inactive High.
Table 12-19. Extended Register HDLC Mode (Ports E and F only) Serial Port x Extended Register Bit(s) 7:5 Value (SEER) (SFER) (Address = 0xCD) (Address = 0xDD) Description (HDLC mode only) 000 NRZ data encoding for HDLC receiver and transmitter. 010 NRZI data encoding for HDLC receiver and transmitter. 100 Biphase-Level (Manchester) data encoding for HDLC receiver and transmitter. 110 Biphase-Space data encoding for HDLC receiver and transmitter.
12.3 Serial Port Interrupt A common interrupt vector is used for the receive and transmit interrupts. There is a separate interrupt request flip-flop for the receiver and transmitter. If either of these flip-flops is set, a serial port interrupt is requested. The flip-flops are set by a rising edge only. The flip-flops are cleared by a pulse generated by an I/O read or write operation as shown in Figure 12-3.
12.4 Transmit Serial Data Timing On transmit, if the interrupts are enabled, an interrupt is requested when the transmit register becomes empty and, in addition, an interrupt occurs when the shift register and transmit register both become empty, that is, when the transmitter becomes idle. The shift register is empty when the last bit is shifted out.
12.5 Receive Serial Data Timing When the receiver is ready to receive data, a falling edge indicates that a start bit must be detected. The falling edge is detected as a different Rx input between two different clocks, the clock being 8x or 16x the baud rate. Once the start bit has been detected, data bits are sampled at the middle of each data bit and are shifted into the receive shift register.
12.6 Clocked Serial Ports Ports A–D can operate in clocked mode. The data line and clock line are driven as shown in Figure 12-4. The data and clock are provided as 8-bit bursts with the LSB shifted out and/or received first. By default the transmit shift register advances on the falling edge of the clock and the receiver samples the data on the rising edge of the clock. The serial port can generate the clock or the clock can be provided externally.
with new incoming data. Similarly, writing the data to the SxAR register causes the transmitter to start a byte transmit operation, eliminating the need for the software to issue the Start Transmit command. The effect of these codes is different, depending on whether the mode is internal clock or external clock. To transmit in internal clock mode, the user must first load the data register (which must be empty) and then store the send code.
answer its interrupts within 20 µs. There will be no slow down if the receiver can answer its interrupt within 1/2 clock or 1.25 µs. If it can answer within 1.5 clocks, or 2.75 µs, the data rate will slow to 44,444 bytes per second. If it can answer in 2.5 clocks or 6.25 µs, the data rate slows to 40,000 bytes per second. If it can answer in 3.5 clocks or 8.75 µs, the data rate will slow to 36,363 bytes per second, and so forth.
12.7 Clocked Serial Timing 12.7.1 Clocked Serial Timing With Internal Clock For synchronous serial communication, the serial clock can be either generated by the Rabbit or by an external device. The timing diagram in Figure 12-6 below can be applied to both full-duplex and half-duplex clocked serial communication where the serial clock is generated internally by the Rabbit. Other SPI compatible clock modes supported by the Rabbit 3000 are shown in Figure 12-5.
Figure 12-8 shows the timing relationship among perclk, the external serial clock, and data receive. Note that RxA is sampled by the rising edge of perclk. perclk CLKA (Ext.) RxA Valid Figure 12-8. Synchronous Serial Data Receive Timing with External Clock (Mode 00) When clocking the Rabbit externally, the maximum serial clock frequency is limited by the amount of time required to synchronize the external clock with the Rabbit perclk.
12.8 Synchronous Communications on Ports E and F Serial Port E and F are a dual-function serial ports that can be used in either asynchronous or HDLC mode. Four bytes of buffering are available for both receiver and transmitter to reduce interrupt overhead. An interrupt is generated whenever at least one byte is available in the receiver buffer and every time a byte is removed from the transmitter buffer. Serial Port E is clocked by the output of Timer A2 and Serial Port F by A3.
the current receive frame is not needed (because it is addressed to a different station, for example) a Flag Search command is available. This command forces the receiver to ignore the incoming data stream until another Flag is received.
Serial Clock NRZ Data NRZI NRZI Biphase-Level Biphase-Space Biphase-Space Biphase-Mark Biphase-Mark data "1" "0" "1" "1" "0" "0" "1" "0" In HDLC mode the internal clock comes from the output of Timer A2. This timer output is divided by sixteen to form the transmit clock, and is fed to the Digital Phase-Locked Loop (DPLL) to form the receive clock. The DPLL is basically just a divide-by-16 counter that uses the timing of the transitions on the receive data stream to adjust its count.
clock rate must be very small, and depends on the longest possible run of zeros in the received frame. NRZI encoding guarantees at least one transition every six bits (with the inserted zeros). Since the DPLL can adjust by two counts every bit cell, the maximum difference between the sending data rate and the DPLL output clock rate is 1/48 (~2%). With Biphase data encoding (either -Level, -Mark or -Space), the DPLL runs only as long as transitions are present in the receive data stream.
With NRZ and NRZI encoding all transitions occur on bit-cell boundaries and the data should be sampled in the middle of the bit cell. If a transition occurs after the expected bitcell boundary (but before the midpoint) the DPLL needs to lengthen the count to line up the bit-cell boundaries. This corresponds to the “add one” and “add two” regions shown. If a transition occurs before the bit cell boundary (but after the midpoint) the DPLL needs to shorten the count to line up the bit-cell boundaries.
12.9 Serial Port Software Suggestions The receiver and transmitter share the same interrupt vector, but it is possible to make the receive and transmit interrupt service routines (ISRs) separate by dispatching the interrupt to either of two different routines. This is desirable to make the ISR less complex and to reduce the interrupt off time. No interrupts will be lost since distinct interrupt flip-flops exist for receive and transmit.
LD (HL),A ; 6 update the in pointer IOI LD A,(SCDR) ; 11 get data register port C, clears interrupt request IPRES ; 4 restore the interrupt priority ; 68 clocks to here ; to level before interrupt took place ; more interrupts could now take place, ; but receiver data is in registers ; now handle the rest of the receiver interrupt routine LD HL,bufbase ; 6 LD D,0 ; 6 ADD HL,DE ; 2 location to store data LD (HL),A ; 6 put away the data byte POP DE ; 7 POP HL ; 7 POP AF ; 7 RET ; 8 from interrupt ; 117 clocks
2. Clear bit 4 of the Parallel Port C function register so that the output no longer comes from the serial port. Of course, this should not be done until the transmitter is idle. A similar procedure can be used if the serial port is set up to use alternate output pins on port D. Only Serial Ports A and B can use alternate outputs on Parallel Port D. If an RS-485 driver is being used, dummy characters can be transmitted by disabling the driver after the stop bit has been sent.
Figure 12-9 illustrates the standard asynchronous serial output patterns. stop bit 0 7 data bits start bit 9th bit low Character with 9th bit low 0 start bit 7 Character w/o 9th bit low 0 start bit stop bit stop bit 7 Character w. 9th bit high 9th bit high Generated by a Write to SxLR Signal shown at output pin on processor. A “1” is high. Figure 12-9. Asynchronous Serial Output Patterns 12.9.
12.9.8 Supporting 9th Bit Communication Protocols This section describes how 9th bit communication protocols work. 9th bit communication protocols are supported by processors such as the 8051 and the Z180, and by companies such as Cimentrics Technology. The data bytes have an extra 9th bit appended where a parity bit would normally be placed.
the receiving interrupt service routine to detect this gap, it is suggested that dummy characters be transmitted to help detect the gap. This can be done in the following manner. The transmitter starts transmitting dummy characters when the first character interrupt is received. Each time there is an interrupt, either receiver data register full or transmitter data register empty, a dummy character is transmitted if the transmitter data register is empty.
198 Rabbit 3000 Microprocessor
13. RABBIT SLAVE PORT When a Rabbit microprocessor is configured as a slave, Parallel Port A and certain other data lines are used as communication lines between the slave and the master. The slave unit is a Rabbit configured as a slave. The master can be another Rabbit or any other type of processor. Rabbits configured as slaves can themselves have slaves. The master and slave communicate with each other via the slave port.
A status register can be read by either the slave or the master. The status register has full/ empty bits for each of the six registers. A data register is considered full when it is written to by whichever side is capable of writing to it. If the same register is then read by either side it is considered to be empty. The flag for that register is thus set to a "1" when the register is written to, and the flag is set to a "0" when the register is read.
The following table explains the parameters used in Figure 13-2.
Master writes SPD0R Slave inbound interrupt requested Visible in status register Slave writes status register Slave writes SPD0R /SLAVEATTN (PB7) Visible in status register Master writes status register Figure 13-3. Slave Port Handshaking and Interrupts Figure 13-4 shows a sample connection of two slave Rabbits to a master Rabbit. The master drives the slave reset line for both slaves and provides the main processor clock from its own clock.
Master Rabbit D0–D7 /IORD /IOWR A0 A1 CLK portout INT0A /I7 First Slave Rabbit SD0–SD7 + /SRD /SWR SA0 SA1 SMODE0 /XTALB1 SMODE1 /RESET /SLAVEATTN /SCS INT1A /I6 Second Slave Rabbit + Reset Pulldown SMODE0 /SLAVEATTN /SCS SMODE1 Figure 13-4. Typical Connection Slave Rabbit to Master Rabbit The slave port lines are shown in Figure 13-1. The function of these lines is described below. • SD0–SD7—These are bidirectional data lines, and are generally connected to the data bus of the master processor.
• /SLAVEATTN—This line is set low (asserted) if the slave writes to the SPD0R register. This line is set high if the master writes anything to the slave status register. This line is usually connected to cause the master to be interrupted when it goes low. The data lines of the slave port are shared with Parallel Port A that uses the same package pins. The slave port can be enabled, and Parallel Port A be disabled, by storing an appropriate code in the slave port control register (SCR).
If the user for some reason wants to depart from the suggested protocols and poll a register while waiting for the other side to write something to the register, the user should be aware that all the bits might not change at the exact same time when the result changes, and a transitional value could be read from the register where some bits have changed to the new value and others have not.
Bits 1,0—This 2-bit field sets the priority of the slave port interrupt. The interrupt is disabled by (0,0). Table 13-3 describes the slave port status register. The status register has 6 bits that are set if the particular register is full. That means that the register has been written by the processor that can write to it but it has not been read by the processor that can read it. The bits for SPD0R are used to control the slave interrupt and the handshaking lines as shown in Figure 13-3. Table 13-3.
require a speciality processor. The slave processor can process data to perform pattern recognition or to extract a specific parameter from a data stream. 13.3.2 Master-Slave Messaging Protocol In this protocol the master sends messages to the slave and receives an acknowledgement message. The protocol can be polled or interrupt driven. Generally, the master sends a message that has a message type code, perhaps a byte count, and the text of the message.
for this.) Once the software is loaded into the slave, the slave can begin to perform its function. As a simple example, suppose that the slave is to be used as a four-port UART. It has the capability to send or receive characters on any of its four serial ports. Leaving aside the question of setup for parameters, such as the baud rate, we could define a protocol as follows.
14. RABBIT 3000 CLOCKS The Rabbit 3000 normally uses two clocks, the main clock and the 32.768 kHz clock. The 32.768 kHz clock is needed for the battery-backable clock, the watchdog timer, and the cold-boot function. The main oscillator provides the run-time clock for the microprocessor. Figure 14-1 shows the main oscillator circuit. TN235, External 32.768 kHz Oscillator Circuits, provides further information on the 32.
14.1 Low-Power Design The power consumption is proportional to the clock frequency and to the square of the operating voltage. Thus, operating at 3.3 V instead of 5 V will reduce the power consumption by a factor of 10.9/25, or 43% of the power required at 5 V. The clock speed is reduced proportionally to the voltage at the lower operating voltage. Thus the clock speed at 3.3 V will be about 2/3 of the clock speed at 5 V. The operating current is reduced in proportion to the operating voltage.
15. EMI CONTROL EMI or electromagnetic interference from unintentional radiation is of concern to the microprocessor system designer. One concern is passing the tests sometimes required by the U.S. Federal Communications Commission (FCC) or by the European EMC Directive. For example, in the U.S.
15.1 Power Supply Connections and Board Layout Refer to Technical Note TN221, PC Board Layout Suggestions for the Rabbit 3000 Microprocessor, for recommendations on laying out a PC board to minmize EMI emsissions. 15.2 Using the Clock Spectrum Spreader The spectrum spreader is very powerful for reducing EMI because it will reduce all sources of EMI above 100 MHz that are related to the clock by about 15 dB.
Table 15-1. Spread Spectrum Enable/Disable Register Global Clock Modulator 0 Register Bit(s) Value (GCM0R) (Address = 0x0A) Description 0 Enable normal spectrum spreading. 1 Enable strong spectrum spreading. 7 6:0 These bits are reserved. Table 15-2. Spread Spectrum Mode Select Global Clock Modulator 1 Register Bit(s) Value (GCM1R) (Address = 0x0B) Description 0 Disable the spectrum spreader. 1 Enable the spectrum spreader. 7 6:0 These bits are reserved.
so low as to be undetectable, except perhaps for extremely weak stations. The effect of a pure harmonic on TV reception is to create a herringbone pattern created by a harmonic falling within the station’s band. If the spreader is engaged the pattern will disappear unless the station is very weak, in which case the interference will be seen as noise distributed over the screen.
16. AC TIMING SPECIFICATIONS The Rabbit 3000 processor may be operated at voltages between 1.8 V and 3.6 V, and at temperatures from –40°C to +85°C with use possible use over the extended range -55°C to +105°C. For long life it is desirable not to exceed a die temperature of 125°C. Most users will operate the Rabbit at 3.3 V. 16.1 Memory Access Time Required memory address and output enable access time for some important typical cases are given in the table below.
Figure 16-1 illustrates the parameters used to describe memory access time. delay capacitive loading setup time data to clock Figure 16-1. Parameters Used to Describe Memory Access Time Table 16-2 lists the delays in gross memory access time for several values of VDD. Table 16-2. Data and Clock Delays VDD ±10%, Temp, -40°C–+85°C (maximum) Clock to Address Output Delay (ns) 30 pF 60 pF 90 pF Data Setup Time Delay (ns) 3.3 6 8 11 2.7 7 10 2.5 8 1.
Figure 16-2 and Figure 16-3 illustrate the memory read and write cycles. The Rabbit 3000 operates at 2 clocks per bus cycle plus any wait states that might be specified. Memory Read (no wait states) T2 T1 CLK A[19:0] valid Tadr /CSx TCSx TCSx /OEx TOEx D[7:0] TOEx Tsetup valid Thold Memory Write (no extra wait states) T1 Tw T2 CLK A[19:0] /CSx /WEx D[7:0] valid Tadr TCSx TCSx TWEx TWEx valid TDHZV TDVHZ Figure 16-2.
The following memory read time delays were measured. Table 16-3. Memory Read Time Delays Output Capacitance Time Delay 30 pF 60 pF 90 pF Max. clock to address delay (Tadr) 6 ns 8 ns 11 ns Max. clock to memory chip select delay (TCSx) 6 ns 8 ns 11 ns Max. clock to memory read strobe delay (TOEx) 6 ns 8 ns 11 ns Min. data setup time (Tsetup) 1 ns Min. data hold time (Thold) 0 ns The measurements were taken at the 50% points under the following conditions. • T = -40°C to 85°C, V = 3.
Memory Read (no wait states) T2 T1 CLK A[19:0] valid Tadr /CSx /OEx TCSx TCSx TOEx TOEx Tsetup D[7:0] valid Thold Memory Write (no extra wait states) T1 Tw T2 CLK A[19:0] valid Tadr /CSx /WEx D[7:0] TCSx TCSx TWEx TWEx valid TDHZV TDVHZ Figure 16-3.
Figure 16-4 illustrates the sources that create memory access time delays. clock period shortening due to spectrum spreader clock address data out clock to address output data in setup time memory access time output enable (early) memory output enable time Figure 16-4. Sources of Memory Access Time Delays The gross memory access time is 2T, where T is the clock period.
The required memory output enable access time is more complicated since it is affected by the clock doubler delays. The clock doubler setup register creates a nominal delay time ranging from 6 to 20 ns, resulting in a nominal clock low time ranging from 6 to 20 ns. The clock low time depends on internal delays, and is subject to variation arising from process variation, operating voltage and temperature.
The following factors have to be taken into account when calculating the output enable access time required. • The gross output enable access time is T + minimum clock low time (it is assumed that the early output enable option is enabled) This is reduced by the spectrum spreader loss, the time from clock to output for the output enable signal, the data setup time, and a correction for the asymmetry of the original oscillator clock. Example • Clock = 29.49 MHz, • T = 34 ns, • operating voltage is 3.
16.2 I/O Access Time Figure 16-6 illustrates the I/O read and write cycles. External I/O Read (no extra wait states) T1 Tw T2 CLK A[15:0] valid Tadr /CSx /IOCSx TCSx TCSx TIOCSx TIOCSx /IORD TIORD TIORD /BUFEN TBUFEN Tsetup TBUFEN D[7:0] valid Thold External I/O Write (no extra wait states) T1 Tw T2 CLK A[15:0] valid Tadr /CSx /IOCSx /IOWR /BUFEN D[7:0] TCSx TCSx TIOCSx TIOCSx TIOWR TIOWR TBUFEN TBUFEN valid TDHZV TDVHZ Figure 16-6.
The following I/O read time delays were measured. Table 16-5. I/O Read Time Delays Output Capacitance Time Delay 30 pF 60 pF 90 pF Max. clock to address delay (Tadr) 6 ns 8 ns 11 ns Max. clock to memory chip select delay (TCSx) 6 ns 8 ns 11 ns Max. clock to I/O chip select delay (TIOCSx) 6 ns 8 ns 11 ns Max. clock to I/O read strobe delay (TIORD) 6 ns 8 ns 11 ns Max. clock to I/O buffer enable delay (TBUFEN) 6 ns 8 ns 11 ns Min. data setup time (Tsetup) 1 ns Min.
16.3 Further Discussion of Bus and Clock Timing The clock doubler is normally used, except in situations where low-frequency systems are specifically being used. The clock doubler works by oring the clock with a delayed version of itself. The nominal delay varies from 6 to 20 ns, and is settable under program control. Any asymmetry in the oscillator waveform before it is doubled will result in alternate clocks having slightly different periods.
P Oscillator 48% 52% Oscillator delayed and inverted Doubled clock Delay time 0.48P Example Write Cycle 0.52P 0.48P 0.52P address, /CS Data out write pulse early write pulse option address, /CS Example Read Cycle Valid data out from mem output enb early output enb option Figure 16-7.
16.4 Maximum Clock Speeds The Rabbit 3000 is rated for a minimum clock period of 17 ns (commercial specifications) and 18 ns (industrial specifications). The commercial rating calls for a ±5% voltage variation from 3.3 V and a temperature range from -40 to + 70°C. The industrial ratings stretch the voltage variation to ±10% and a temperature range from -40 to + 85°C. This corresponds to maximum clock frequencies of 58.8 MHz (commercial) and 55.5 MHz (industrial).
Example The spreader and doubler are enabled, with 8 ns nominal delay in the doubler. The high and low clock are equal to within 1 ns. This violates the duty cycle requirement by 3 ns since (clock low - clock high) can be as small as -1 ns, but the requirement is that it not be less than 2 ns. Thus, 3 ns must be added to the minimum period of 21 ns, giving a minimum period of 24 ns, and a maximum frequency of 41.6 MHz (commercial).
16.5 Power and Current Consumption With the Rabbit 3000 it is possible to design systems that perform their task with very low power consumption. Unlike competitive processors, the Rabbit 3000 has short chip select features designed to minimize power consumption by external memories, which can easily become the dominant power consumers at low clock frequencies if not well handled.
120 100 I (mA) 80 xtal=25.80 xtal=14.74 60 xtal=11.05 xtal=3.68 40 20 0 0 10 20 30 40 50 60 Clock Frequency (MHz) Figure 16-9. Rabbit 3000 System Current vs. Frequency at 3.3 V 40 35 30 I (mA) 25 xtal=25.80 xtal=14.74 20 xtal=11.05 15 xtal=3.68 10 5 0 0 2 4 6 8 10 12 14 16 Clock Frequency (MHz) Figure 16-10. Rabbit 3000 System Current vs. Frequency at 3.
Lowering the operating voltage will greatly reduce current consumption and power. Dropping to 2.7 V from 3.3 V will result in 70% current consumption and 60% of the power. Further dropping to 1.8 V will reduce current to 40% and power to 20% compared to 3.3 V. Naturally this complicates the selection of memories, especially at 1.8 V.
16.6 Current Consumption Mechanisms The following mechanisms contribute to the current consumption of the Rabbit 3000 while it is operating. 1. A current proportional to voltage and clock frequency that results from the charging of internal and external capacitances. At 3.3 V (see (2) below) approximately 57% of the current is due to charging and 43% is due to crossover current. 2. A crossover current that is proportional to clock frequency and to the overdrive voltage Vc = V × [(V/2) – 0.
16.7 Sleepy Mode Current Consumption In sleepy mode the unit operates from the 32.768 kHz clock, which may be divided down to as slow as 2.048 kHz. The current consumption is given by: Itotal (µA) = 0.32 × V × f + 0.23 × Vc × f + 5 × Vc where f is in kHz, V is the operating voltage, and Vc = V × [(V/2) - 0.7].
16.8 Memory Current Consumption Since there are many different memories available, let’s look at an example using one of the recommended flash and SRAM memories. Flash memory—SST part SST39LF512020, 256K × 8, 45 ns access time. Standby current: nil. • Static Current (chip select low): 3.5 mA @ 3.3 V • Dynamic Current: 7 mA at 14.7 MHz bus speed and 3.3 V The total current is 10 mA at a clock speed of 29.49 MHz or a bus speed of 5 MHz. The static part of the current is computed using 3.
16.9 Battery-Backed Clock Current Consumption When using the suggested tiny logic oscillator, the oscillator and clock consume current as shown in Figure 16-12 below. Normally a resistor is placed in the battery circuit to limit the current to about 3 µA, which results in a voltage setpoint of about 1.7 V. When operating at 3.3 V in sleepy mode, the current of the oscillator and the real-time clock—about 12 µA—must be added. Using the suggested tiny logic oscillator circuit, the external 32.
16.10 Reduced-Power External Main Oscillator The circuit in Figure 16-13 can be used to generate the main clock using less power than with the built-in oscillator buffer. The power consumption is less because of the currentlimiting resistors that cannot be used with the built-in buffer. The 2.2 kΩ series resistor must be reduced as the clock frequency increases, as must be the current-limiting resistors. To Rabbit 3000 XTALA1 +3.3 V 2.2 kW 33 pF SN74HCT1G04DBVR 1 MW 3.
17. RABBIT BIOS AND VIRTUAL DRIVER When a program is compiled by Dynamic C for a Rabbit target, the Virtual Driver is automatically incorporated into the program. Virtual Driver is the name given to some initialization routines and a group of services performed by the periodic interrupt. The Rabbit BIOS, software that handles startup, shutdown and various basic features of the Rabbit, is compiled to the target along with the application program.
17.1.2 BIOS Assumptions The BIOS makes certain assumptions concerning the physical configuration of the processor. Processors are expected to have RAM connected to /CS1, /WE1, and /OE1. Flash is expected to be connected to /CS0, /WE0, and /OE0. (See the Rabbit 3000 Designer’s Handbook Memory Planning chapter if you want to design a board with RAM only.) The crystal frequency is expected to be n*1.8432 MHz. The Rabbit 3000 Designer’s Handbook has a chapter on the Rabbit BIOS with more details. 17.
gram consistency checking or because a part of the program that should be executing periodically is not executing and the watchdog times out. The Virtual Driver’s periodic interrupt hits the hardware watchdog timer with a 2 second time-out. If the periodic interrupt stops working, then the watchdog will time out after 2 seconds. The Virtual Driver provides a number of additional “virtual” watchdog timers for use in other parts of the code that must be entered periodically.
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18. OTHER RABBIT SOFTWARE 18.1 Power Management Support The power consumption and speed of operation can be throttled up and down with rough synchronism. This is done by changing the clock speed or the clock doubler. The range of control is quite wide: the speed can vary by a factor of 16 when the main clock is driving the processor. In addition, the main clock can be switched to the 32.768 kHz clock. In this case, the slowdown is very dramatic, a factor of perhaps 500.
18.2 Reading and Writing I/O Registers The Rabbit has two I/O spaces: internal I/O registers and external I/O registers. 18.2.1 Using Assembly Language The fastest way to read and write I/O registers in Dynamic C is to use a short segment of assembly language inserted in the C program. Access is the same as for accessing data memory except that the instruction is preceded by a prefix (IOI or IOE) to indicate the internal or external I/O space.
18.3 Shadow Registers Many of the registers of the Rabbit’s internal I/O devices are write-only. This saves gates on the chip, making possible greater capability at lower cost. Write-only registers are easier to use if a memory location, called a shadow register, is associated with each writeonly register. To make shadow register names easy to remember, the word shadow is appended to the register name. For example the register GOCR (Global Output Control register) has the shadow GOCRShadow.
ld hl,PDDDRShadow ; point to shadow register ld de,PDDDR ; set de to point to I/O reg set 5,(hl) ; set bit 5 of shadow register ; use ldd instruction for atomic transfer ioi ldd ; (io de)<-(hl) side effect: hl--, de-- In this case, the ldd instruction when used with an I/O prefix provides a convenient data move from a memory location to an I/O location.
Two library functions are provided to read and write the real-time clock: unsigned long int read_rtc(void) ; // read bits 15-46 rtc void write_rtc(unsigned long int time) ; // write bits 15-46 // note: bits 0-14 and bit 47 are zeroed However, it is not intended that the real-time clock be read and written frequently. The procedure to read it is lengthy and has an uncertain execution time. The procedure for writing the clock is even more complicated.
246 Rabbit 3000 Microprocessor
19.
Spreadsheet Conventions ALTD (“A” Column) Symbol Key Flag Description ALTD selects alternate flags f ALTD selects alternate flags and register fr r ALTD selects alternate register s ALTD operation is a special case IOI and IOE (“I” Column) Symbol Key Flag Description b IOI and IOE affect source and destination d IOI and IOE affect destination s IOI and IOE affect source Flag Register Key S Z L/V* C Description * Sign flag affected - Sign flag not affected * Zero flag affected - Zero
Symbols Rabbit Z180 Meaning b b Bit select: 000 = bit 0, 001 = bit 1, 010 = bit 2, 011 = bit 3, 100 = bit 4, 101 = bit 5, 110 = bit 6, 111 = bit 7 cc cc Condition code select: 00 = NZ, 01 = Z, 10 = NC, 11 = C d d 7-bit (signed) displacement. Expressed in two’s complement. dd ww Word register select destination: 00 = BC, 01 = DE, 10 = HL, 11 = SP Word register select alternate: 00 = BC’, 01 = DE’, 10 = HL’ dd’ j 8-bit (signed) displacement added to PC.
19.1 Load Immediate Data Instruction LD IX,mn LD IY,mn LD dd,mn LD r,n clk 8 8 6 4 A r r I S - Z - V - C - Operation IX = mn IY = mn dd = mn r = n 19.
19.5 16-bit Load and Store 20-bit Address Instruction LDP (HL),HL clk 12 A I S Z V C - - - - LDP (IX),HL 12 - - - - LDP (IY),HL 12 - - - - LDP HL,(HL) 10 - - - - LDP HL,(IX) 10 - - - - LDP HL,(IY) 10 - - - - LDP (mn),HL 15 - - - - LDP (mn),IX 15 - - - - LDP (mn),IY 15 - - - - LDP HL,(mn) 13 - - - - LDP IX,(mn) 13 - - - - LDP IY,(mn) 13 - - - - Operation (HL) = L; (HL+1) = H. (Adr[19:16] = A[3:0]) (IX) = L; (IX+1) = H. (Adr[19:16] = A[3:0]) (IY) = L; (IY+1) = H.
19.
ADD IY,yy 4 f - - - * ADD SP,d AND HL,DE AND IX,DE AND IY,DE BOOL HL 4 2 4 4 2 f fr f f fr * * * * * * * * L L L 0 * 0 0 0 0 BOOL IX BOOL IY DEC IX DEC IY DEC ss 4 4 4 4 2 f f r * * - * * - 0 0 - 0 0 - INC IX INC IY INC ss 4 4 2 r - - - - - - - - - - MUL 12 OR OR OR RL 2 4 4 2 fr f f fr * * * * * * * * L L L L 0 0 0 * 2 2 4 4 4 fr fr f f fr * * * * * * * * * * L L L L V * * * * * HL,DE IX,DE IY,DE DE RR DE RR HL RR IX RR IY SBC HL,ss - - - - IY = IY + yy -- yy=BC, DE
CP* n CP* r OR (HL) OR (IX+d) OR (IY+d) OR n OR r SBC* (IX+d) SBC* (IY+d) SBC* A,(HL) SBC* A,n SBC* A,r SUB (HL) SUB (IX+d) SUB (IY+d) SUB n SUB r XOR (HL) XOR (IX+d) XOR (IY+d) XOR n XOR r 4 2 5 9 9 4 2 9 9 5 4 2 5 9 9 4 2 5 9 9 4 2 f * * V * f * * V * fr s * * L 0 fr s * * L 0 fr s * * L 0 fr * * L 0 fr * * L 0 fr s * * V * fr s * * V * fr s * * V * fr * * V * fr * * V * fr s * * V * fr s * * V * fr s * * V * fr * * V * fr * * V * fr s * * L 0 fr s * * L 0 fr s * * L 0 fr * * L 0 fr * * L 0 A A A A A A
19.13 8-bit Fast A Register Operations Instruction CPL NEG RLA RLCA RRA RRCA clk 2 4 2 2 2 2 A I S Z V C r - - - fr * * V * fr - - - * fr - - - * fr - - - * fr - - - * Operation A = ~A A = 0 - A {CY,A} = {A,CY} A = {A[6,0],A[7]}; CY = A[7] {A,CY} = {CY,A} A = {A[0],A[7,1]}; CY = A[0] 19.
SLA r SRA (HL) 4 10 fr * * L * f b * * L * SRA (IX+d) 13 f b * * L * SRA (IY+d) 13 f b * * L * SRA r SRL (HL) 4 10 fr * * L * f b * * L * SRL (IX+d) 13 f b * * L * SRL (IY+d) 13 f b * * L * SRL r 4 fr * * L * r = {r[6,0],0}; CY = r[7] (HL) = {(HL)[7],(HL)[7,1]}; CY = (HL)[0] (IX+d) = {(IX+d)[7], (IX+d)[7,1]}; CY = (IX+d)[0] (IY+d) = {(IY+d)[7], (IY+d)[7,1]}; CY = (IY+d)[0] r = {r[7],r[7,1]}; CY = r[0] (HL) = {0,(HL)[7,1]}; CY = (HL)[0] (IX+d) = {0,(IX+d)[7,1]}; CY = (IX+d)[0] (IY+d
19.
19.19 Privileged Instructions The privileged instructions are described in this section. Privilege means that an interrupt cannot take place between the privileged instruction and the following instruction. The three instructions below are privileged.
20. DIFFERENCES RABBIT VS. Z80/Z180 INSTRUCTIONS The Rabbit is highly code compatible with the Z80 and Z180, and it is easy to port non I/O dependent code. The main areas of incompatibility are instructions that are concerned with I/O or particular hardware implementations. The more important instructions that were dropped from the Z80/Z180 are automatically simulated by an instruction sequence in the Dynamic C assembler. A few fairly useless instructions have been dropped and cannot be easily simulated.
The following instructions use different register names. LD LD LD LD A,EIR EIR,A IIR,A A,IIR ; was R register ; was I register The following Z80/Z180 instructions have been dropped and are not supported. Alternative Rabbit instructions are provided.
21.
Symbols Rabbit Z180 b b cc cc d d dd ww Meaning Bit select: 000 = bit 0, 010 = bit 2, 100 = bit 4, 110 = bit 6, 001 = bit 1, 011 = bit 3, 101 = bit 5, 111 = bit 7 Condition code select: 00 = NZ, 01 = Z, 10 = NC, 11 = C 7-bit (signed) displacement. Expressed in two’s complement. Word register select destination: 00 = BC, 01 = DE, 10 = HL, 11 = SP Word register select alternate: 00 = BC ', 01 = DE ', 10 = HL ' dd' j 8-bit (signed) displacement added to PC.
Instruction Byte 1 Byte 2 ADC A,(HL) 10001110 ADC A,(IX+d) 11011101 10001110 ADC A,(IY+d) 11111101 10001110 ADC A,n 11001110 ----n--ADC A,r 10001-rADC HL,ss 11101101 01ss1010 ADD A,(HL) 10000110 ADD A,(IX+d) 11011101 10000110 ADD A,(IY+d) 11111101 10000110 ADD A,n 11000110 ----n--ADD A,r 10000-rADD HL,ss 00ss1001 ADD IX,xx 11011101 00xx1001 ADD IY,yy 11111101 00yy1001 ADD SP,d 00100111 ----d--ALTD 01110110 AND (HL) 10100110 AND (IX+d) 11011101 10100110 AND (IY+d) 11111101 10100110 AND HL,DE 11011100 AND
Instruction Byte 1 Byte 2 Byte 3 EX AF,AF' 00001000 EX DE,HL 11101011 EX DE',HL 11100011 EX DE,HL' 01110110 11100011 EX DE',HL' 01110110 11100011 EXX 11011001 INC (HL) 00110100 INC (IX+d) 11011101 00110100 ----d--INC (IY+d) 11111101 00110100 ----d--INC IX 11011101 00100011 INC IY 11111101 00100011 INC r 00-r-100 INC ss 00ss0011 ss= 00-BC, 01-DE, 10-HL, 11-SP IOE 11011011 IOI 11010011 IPSET 0 11101101 01000110 IPSET 1 11101101 01010110 IPSET 2 11101101 01001110 IPSET 3 11101101 01011110 IPRES 11101101 01
Instruction Byte 1 LD A,(BC) LD A,(DE) LD A,(mn) 00001010 00011010 00111010 LD A,EIR LD A,IIR LD A,XPC LD dd,(mn) LD dd',BC LD dd',DE LD dd,mn LD bc,mn LD de,mn LD hl,mn LD sp,mn LD EIR,A LD HL,(HL+d) LD HL,(IX+d) LD HL,(IY+d) LD HL,(mn) LD HL,(SP+n) LD HL,IX LD HL,IY LD IIR,A LD IX,(mn) LD IX,(SP+n) LD IX,HL LD IX,mn LD IY,(mn) LD IY,(SP+n) LD IY,HL LD IY,mn LD r,(HL) LD r,(IX+d) LD r,(IY+d) LD r,g LD r,n LD SP,HL LD SP,IX LD SP,IY LD XPC,A LDD LDDR LDI LDIR LDP (HL),HL LDP (IX),HL LDP (IY),HL LDP (mn)
Instruction Byte 1 Byte 2 LDP HL,(HL) LDP HL,(IX) LDP HL,(IY) LDP HL,(mn) LDP IX,(mn) LDP IY,(mn) LJP nbr,mn LRET MUL NEG NOP OR (HL) OR (IX+d) OR (IY+d) OR HL,DE OR IX,DE OR IY,DE OR n OR r POP IP POP IX POP IY POP zz PUSH IP PUSH IX PUSH IY PUSH zz RES b,(HL) RES b,(IX+d) RES b,(IY+d) RES b,r RET RET f RETI RL (HL) RL (IX+d) RL (IY+d) RL DE RL r RLA RLC (HL) RLC (IX+d) RLC (IY+d) RLC r RLCA RR (HL) RR (IX+d) RR (IY+d) RR DE RR HL RR IX RR IY 11101101 11011101 11111101 11101101 11011101 11111101 110001
Instruction Byte 1 RR r 11001011 RRA 00011111 RRC (HL) 11001011 RRC (IX+d) 11011101 RRC (IY+d) 11111101 RRC r 11001011 RRCA 00001111 RST v 11-v-111 SBC (IX+d) 11011101 SBC (IY+d) 11111101 SBC A,(HL) 10011110 SBC A,n 11011110 SBC A,r 10011-rSBC HL,ss 11101101 SCF 00110111 SET b,(HL) 11001011 SET b,(IX+d) 11011101 SET b,(IY+d) 11111101 SET b,r 11001011 SLA (HL) 11001011 SLA (IX+d) 11011101 SLA (IY+d) 11111101 SLA r 11001011 SRA (HL) 11001011 SRA (IX+d) 11011101 SRA (IY+d) 11111101 SRA r 11001011 SRL (HL) 11
268 Rabbit 3000 Microprocessor
APPENDIX A. THE RABBIT PROGRAMMING PORT The programming port provides a standard physical and electrical interface between a Rabbit-based system and the Dynamic C programming platform. A special interface cable and converter connects a PC serial port to the programming port. The programming port is implemented by means of a 10-pin standard 2 mm connector. (Of course the user can change the physical implementation of the connector if he so desires.
A.1 Use of the Programming Port as a Diagnostic/Setup Port The programming port, which is already in place, can serve as a convenient communications port for field setup, diagnosis or other occasional communication need (for example, as a diagnostic port). There are several ways that the port can be automatically integrated into the user’s software scheme.
an asynchronous signal suitable for the PC. Since the target controls the clock for both send and receive, the data transmission proceeds at a rate controlled by the target board under development. This scheme does not allow for an interrupt, and it is not desirable to use up an external interrupt for this purpose. The serial port may be used, if desired, During program load because there is no conflict with the user’s program at compile load time. However, the user’s program will conflict during debugging.
Table A-1. Preliminary Crystal Frequencies, Memory Access Times, and Baud Rates Crystal Frequency (MHz) Doubled Frequency (MHz) Doubled Period (ns) Access Time (ns) 1.8432 3.6864 271 522 4 3.6864 7.3728 136 257 8 7.3728 14.7456 68 124 16 9.216 18.432 54 97 20 11.0592 22.1184 45 79 24 12.9024 25.8048 39 67 28 14.7456 29.4912 34 57 32 18.432 36.864 27 44 40 22.1184 44.2368 23 35 48 25.8048 51.
APPENDIX B. RABBIT 3000 REVISIONS Since its release, the Rabbit 3000 microprocessor has gone through one revision. The revision reflects bug fixes, improvements, and the introduction of new features. All Rabbit 3000 revisions are pin-compatible, and transparently replace previous versions of the chip. The Rabbit 3000 has been supplied in the following versions. 1. Original Rabbit 3000—Available in two packages and identified by IL1T for the LQFP package and IZ1T for the TFBGA package.
2. First revision (Rabbit 3000A)—Available in two packages and identified by IL2T for the LQFP package and IZ2T for the TFBGA package. This version began shipping in August 2003. All the bugs in the original Rabbit 3000 were fixed. The Rabbit 3000A contains a number of new features and improvements. (a) A new mode of operation known as System/User mode was added.
(l) The quadrature decoder hardware can be configured to use a 10-bit counter in place of the existing 8-bit counter. (m)An option was added to alternatively multiplex PWM outputs, slave chip select (/SCS), and Serial Ports E and F transmit and receive clocks on other pins. (n) The Schmitt trigger IC normally required for the low power 32.768 kHz oscillator circuit is now integrated inside the Rabbit 3000A.
B.1 Discussion of Fixes and Improvements Table B-1 lists the bug fixes, improvements, and additions for the various revisions of the Rabbit 3000. Table B-1. Summary of Rabbit 3000 Improvements and Fixes Description Rabbit 3000 Rabbit 3000A (IL1T/IZ1T) (IL2T/IZ2T) ID Registers for version/revision identification. 276 X X System/User mode. X Memory protection scheme. X Stack protection. X RAM segment relocation. X Secondary watchdog timer. X Multiply-add and multiply-subtract.
B.1.1 Rabbit Internal I/O Registers Table B-2 summarizes the reset state of the new I/O registers added in the Rabbit 3000A revision. Table B-3 summarizes the reset state of the existing I/O registers with new features. Table B-2.
Table B-2.
Table B-3.
B.1.2 Peripheral and ISR Address Table B-4.
Table B-4.
B.1.3 Revision-Level ID Register Two read-only registers are provided to allow software to identify the Rabbit microprocessor and recognize the features and capabilities of the chip. Five bits in each of these registers are unique to each version of the chip. One register identifies the CPU (GCPU), and the other register is reserved for revision identification (GREV). The CPU identification (GCPU) of all revisions of the Rabbit 3000 microprocessor is the same.
B.1.4 System/User Mode By default, all of the hardware is accessible by the programmer. However, if a control bit in the Enable Dual Mode Register (EDMR) is set to one, two operating modes, System and User, become available. The System mode is just like the normal operating mode, but the User mode restricts program access to the hardware and to the System mode. Individual peripherals may be enabled for User mode access in the User Enable registers listed below.
B.1.5 Memory Protection The ability to inhibit writes to physical memory was added. The sixteen 64 KB physical memory blocks can be individually protected, and two of those blocks can additionally be subdivided and protected at a granularity of 4 KB. When a write is attempted, a new Priority 3 write-protection interrupt request is generated. The write-protection can be enabled for the User mode only or for all modes (see Appendix C for more information).
Table B-7. Write Protect Low Register Write Protect Low Register Bit(s) Value (WPLR) (Address = 0x0460) Description 0 Disable 64K write-protect for physical address 0x70000–0x7FFFF. 1 Enable 64K write-protect for physical address 0x70000–0x7FFFF. 0 Disable 64K write-protect for physical address 0x60000–0x6FFFF. 1 Enable 64K write-protect for physical address 0x60000–0x6FFFF. 0 Disable 64K write-protect for physical address 0x50000–0x5FFFF.
Table B-8. Write Protect High Register Write Protect High Register Bit(s) Value (WPHR) (Address = 0x0461) Description 0 Disable 64K write-protect for physical address 0xF0000–0xFFFFF. 1 Enable 64K write-protect for physical address 0xF0000–0xFFFFF. 0 Disable 64K write-protect for physical address 0xE0000–0xEFFFF. 1 Enable 64K write-protect for physical address 0xE0000–0xEFFFF. 0 Disable 64K write-protect for physical address 0xD0000–0xDFFFF.
Table B-10.
Table B-11.
B.1.6 Stack Protection Stack overflow and underflow can now be detected. Low and high stack limits can be set on 256-byte boundaries. When a stack-relative memory access occurs within 16 bytes of these limits (or outside of them), a new Priority 3 stack violation interrupt occurs. The 16byte buffer exists to allow stack protection even if the stack is placed against a memory segment boundary. Figure B-2 shows one possible stack layout.
The stack protection registers are listed in Table B-12, Table B-13, and Table B-14. Table B-12. Stack Limit Control Register Stack Limit Control Register Bit(s) Value 7:1 (STKCR) (Address = 0x0444) Description These bits are reserved and should be written with zeros. 0 Disable stack-limit checking. 1 Enable stack-limit checking. 0 Table B-13. Stack Low Limit Register Stack Low Limit Register Bit(s) Value (STKLLR) (Address = 0x0445) Description Lower limit for stack limit checking.
B.1.7 RAM Segment Relocation Normally when instruction/data separation is enabled, instructions are stored in flash memory and data are stored in RAM memory. This can present a problem for the Interrupt Service Routine area, which often requires run-time modification. The RAM Segment Register (RAMSR) allows a 1, 2, or 4 KB segment of the logical memory space to be mapped as data would be mapped, even for program execution. Table B-15.
B.1.8 Secondary Watchdog Timer The secondary watchdog timer (SWDT) is an eight-bit modulo n + 1 counter clocked by the 32.768 kHz clock. The timer is off by default, and is enabled by writing a 0x5F to the WDTCR. The secondary watchdog timer register (SWDTR) holds the time constant value. Depending on the value loaded into the SWDTR, the timer can request an interrupt anywhere from 30.5 µs to 7.8 ms.
B.1.9 New Opcodes Eight new opcodes were added to the Rabbit 3000A. UMA and UMS allow multiply-andadd and multiply-and-subtract operations on large integers, and were added to speed up common cryptographic math used in public-key calculations. The remaining six expand the block copy operations available, especially to and from I/O addresses (internal and external). These opcodes are listed in Table B-18. Table B-18.
B.1.9.2 New Block Copy Opcodes The LDxR family of block move opcodes has been expanded. In the Rabbit 3000 processor, block copy operations could only be done between memory addresses, or from memory to an I/O address. In addition, the destination I/O address would increment (or decrement if using LDDR) after each byte, making the block copy opcodes effectively useless for repeated reads or writes to a peripheral (for example, a device on the external I/P bus).
B.1.10 Expanded I/O Memory Addressing In the Rabbit 3000, only the lower 8 bits of an I/O address were decoded. To provide room for new peripherals, this was expanded to 16 bits. To ensure backwards compatibility, the processor always comes up in 8-bit I/O address mode; the 16-bit I/O address mode needs to be enabled in the MMIDR register by setting bit 7 to 1. The updated MMIDR register is listed in Table B-20. NOTE: Bits 7 was always written with a zero in the original Rabbit 3000 chip. Table B-20.
B.1.11 External I/O Improvements Three new features have been added to the external I/O strobes: the ability to invert the strobe signal, the ability to shorten a read strobe by one clock, and the ability to direct a strobe to either the alternate I/O bus (if enabled) or the memory bus. The new control bits for the external I/O strobes are listed in Table B-21. NOTE: Bits [1:0] were always written with zero in the original Rabbit 3000 chip. Table B-21.
B.1.12 Short Chip Select Timing for Writes The Rabbit 3000 provided the ability to produce shorter chip select strobes for reads when in a reduced-speed mode. A new feature has been added to produce short chip select strobes for writes as well, and can be controlled by the GPCSR register. The new control bit for the short chip selects are listed in Table B-22. NOTE: Bit 3 was always written with zero in the original Rabbit 3000 chip. Table B-22.
B.1.12.1 Clock Select and Power Save Modes Table B-24 outlines the power save modes available in the Rabbit 3000A. The GCSR is shown in Table B-23 for reference. Table B-23. Global Control/Status Register Global Control/Status Register Bit(s) 7:6 (rd-only) (GCSR) Value (Address = 0x00) Description 00 No reset or watchdog timer time-out since the last read. 01 The watchdog timer timed out. These bits are cleared by a read of this register. 10 This bit combination is not possible.
B.1.12.2 Short Chip Select Timing When short chip selects are enabled for read cycles, the chip select signals are active only for the last part of the bus cycle. Wait states are inserted between T1 and T2, so this will have no effect on the duration of the chip select signals in this mode. The timing diagrams below illustrate the actual timing for the different divided cases. In these cases the chip selects are two clock cycles (of the fast oscillator) long.
T1 T2 o s c illa t o r c lo c k ADD R Valid DAT A /C S x /O E x d iv i de - by - 6 m o de Figure B-4. Short Chip Select Timing: CLK/6, Read Operation T1 T2 oscillator clock ADDR Valid DATA /CSx /OEx divide-by-4 mode Figure B-5.
T1 T2 oscillato r clock ADD R Valid DATA /CSx /OEx divide -by-2 mo de Figure B-6.
When operating from the 32 kHz oscillator, the same options are available, but the timing is somewhat different. This is illustrated in the diagrams below for the four different cases. In these case the chip selects are one clock cycle (of the 32 kHz clock) long. T1 T2 32KHz 32 kHz clock ADDR Valid DATA MEMCSxB /CSx MEMOExB /OEx 22KHz kHz operation Figure B-7. Short Chip Select Timing: 2 kHz, Read Operation T1 T2 32 kHz clock ADDR Valid DATA /CSx /OEx 4 kHz operation Figure B-8.
T1 T2 32 kHz clock ADD R Valid DAT A /CSx /O Ex 8 kHz ope ratio n Figure B-9. Short Chip Select Timing: 8 kHz, Read Operation T1 T2 32 kHz clock ADD R Valid DATA /CSx /OEx 16 kHz operatio n Figure B-10.
T1 T2 32 kHz clock ADD R Valid DATA /CSx /OEx 32 kHz operatio n Figure B-11.
In the case of write cycles, the chip select signals are active only around the trailing edge of the write signal. Wait states are inserted between T1 and T2, and this will have no effect on the duration of the chip select signals in this mode. The timing diagrams below illustrate the actual timing for the different divided cases. In these cases the chip selects are active for two clock cycles before and two clock cycles after the trailing edge of the write signal.
T1 TWA T2 oscillator clock ADDR Valid DATA /CSx /WEx divide-by-6 mode Figure B-13. Short Chip Select Timing: CLK/6, Write Operation T1 TW A T2 o s c illa t o r c lo c k ADD R V a li d DATA /C S x /W E x d iv ide - by - 4 m o de Figure B-14.
T1 TWA T2 oscillator clock ADDR Valid DATA /CSx /WEx divide-by-2 mode Figure B-15.
The timing diagrams below illustrate the actual timing for the 32KHz cases of write cycles. In these cases the chip selects are active for one clock cycle before and one clock cycle after the trailing edge of the write signal. T1 TWA T2 32 32KHz kHz clock ADDR Valid DATA MEMCSxB /CSx MEMWExB /WEx 2 kHz operation 2KHz operation Figure B-16. Short Chip Select Timing: 2 kHz, Write Operation T1 TWA T2 32 kHz clock ADDR Valid DATA /CSx /WEx 4 kHz operation Figure B-17.
T1 TWA T2 32 kHz clock ADDR Valid DATA /CSx /WEx 8 kHz operation Figure B-18. Short Chip Select Timing: 8 kHz, Write Operation T1 TWA T2 32 kHz clock ADDR Valid DATA /CSx /WEx 16 kHz operation Figure B-19.
T1 TWA T2 32 kHz clock ADDR Valid DATA /CSx /WEx 32 kHz operation Figure B-20.
B.1.13 Pulse Width Modulator Improvements Several new features have been added to the pulse width modulator. First, a new PWM interrupt can be set up to be requested on every PWM cycle, every other cycle, every fourth cycle, or every eighth cycle. The setup for this interrupt is done in the PWL0R and PWL1R registers, listed in Table B-25 and Table B-26.
Table B-25. PWM LSB 0 Register PWM LSB 0 Register (PWL0R) (Address = 0x0088) Bit(s) Value 7:6 write 5:4 00 Normal PWM operation. 01 Suppress PWM output seven out of eight iterations of PWM counter. 10 Suppress PWM output three out of four iterations of PWM counter. 11 Suppress PWM output one out of two iterations of PWM counter. 3 2:1 Description The least significant two bits for the Pulse Width Modulator count are stored. This bit is ignored and should be written with zero.
Table B-27. PWM LSB 2 and 3 Registers PWM LSB x Register (PWL2R) (Address = 0x008C) (PWL3R) (Address = 0x008E) Bit(s) Value 7:6 write 5:4 00 Normal PWM operation. 01 Suppress PWM output seven out of eight iterations of PWM counter. 10 Suppress PWM output three out of four iterations of PWM counter. 11 Suppress PWM output one out of two iterations of PWM counter. 3:1 Description The least significant two bits for the Pulse Width Modulator count are stored.
B.1.14 Quadrature Decoder Improvements The quadrature decoder counters can now be expanded to 10 bits instead of 8 bits. This is controlled by bit 5 in QDCR, listed in Table B-28. The additional two bits can be read in the QDCxHR registers, listed in Table B-29. NOTE: Bit 5 of QDCR was always written with a zero in the original Rabbit 3000 chip. Table B-28.
I input Q input Cnt (8 bit) FF 00 01 02 03 04 05 06 07 08 07 06 05 04 03 02 01 00 FF Cnt (10 bit) 3FF 000 001 002 003 004 005 006 007 008 007 006 005 004 003 002 001 000 3FF Interrupt Figure B-22.
B.2 Pins with Alternate Functions The Rabbit 3000A provides greater flexibility for multiplexing I/O functions to other pins. The following alternate connections were introduced in the Rabbit 3000A for these peripherals, and are indicated by an asterisk in Table 5-2.
APPENDIX C. SYSTEM/USER MODE The Rabbit 3000A is the first Rabbit microprocessor to incorporate a “system/user mode.” The purpose of the System/User mode is to provide two tiers of control in the CPU: system, which provides full access to all processor resources; and user, a more restricted mode. Table C-1 describes the essential differences between the System mode and the User mode. The System mode is essentially the same as the normal operation of the Rabbit 3000 and earlier processors. Table C-1.
C.1 System/User Mode Opcodes Seven new opcodes have been added to support the System/User mode, and are listed in Table C-2. All but IDET are placed in previously empty opcode table assignments. IDET shares the value of LD E,E in the opcode table, and will perform that operation when the System/User mode is disabled, or when it is enabled and in the System mode. In addition, if the ALTD prefix appears before the opcode, LD E’,E is always executed instead.
C.2 System/User Mode Registers Table C-3 lists the new I/O registers added to support the System/User mode. The Enable Dual Mode Register (EDMR) is used to enable and disable the System/User mode. All other I/O registers listed in the table are “User mode enable” registers for each peripheral. On startup, User mode access is not allowed to all the peripherals (all writes to I/O registers for that peripheral are ignored), but can be enabled by writing to the appropriate register.
The I/O banks on Port E (enabled for the User mode by IBUER) have a slightly different operation in the User mode. Disabling user access to a given I/O bank not only causes writes to the corresponding IBxCR register to be ignored in the User mode, but also inhibits the strobe associated with that I/O bank. Access to the internal I/O registers listed in Table C-4 is always denied in the User mode. Table C-4.
C.3 Interrupts When enabled for User mode access, a peripheral interrupt (if it is capable of generating an interrupt) can only be requested at Interrupt Priority Level -2 or -1. Interrupts (and RSTs and SYSCALL) all enter the System mode automatically. There will be times, however, that an interrupt should be handled in the User mode. The solution to this is for the System mode interrupt vector to reenter User mode before calling the User mode interrupt handler.
C.3.1 Peripheral Interrupt Prioritization Most interrupts can be programmed to occur at any of three priority levels, but several are restricted to Level 3 (the highest priority) only. The interrupts restricted to Level 3 are system mode violation, stack limit violation, write protection violation, and the secondary watchdog. In addition, any interrupt assigned to User mode is prevented (by hardware) from requesting a Level 3 interrupt.
Table C-5. Interrupts—Priority and Action to Clear Requests Priority Highest Lowest Interrupt Source Action required to clear the interrupt System Mode Violation Automatically cleared by the interrupt acknowledge. Stack Limit Violation Automatically cleared by the interrupt acknowledge. Write Protection Violation Automatically cleared by the interrupt acknowledge. Secondary Watchdog Restart the Secondary Watchdog by writing to WDTCR.
C.4 Using the System/User Mode The System/User mode is designed to work with new features in the Rabbit 3000A (memory protection, stack protection, etc.) to provide a seamless framework for protection of critical code. However, there are many levels at which the System/User mode can be used; some examples are described here. C.4.
C.4.2 Mixed System/User Mode Operation This mode is similar to the previous mode, but with some portions of the program written for the System mode—for example, peripheral interrupts where latency is critical. By keeping the System mode code sections small, potential system crashes are still minimized. An overview of this level of operation is shown in Figure C-3.
C.4.3 Complete Operating System This section describes a “full” use of the System/User mode—separating all common functions into a System mode “operating system” while letting the application-specific code run in the User mode.By default, the System mode handles all peripherals and interrupts, as well as high-level interfaces such as a flash file system. However, the processor will be running the application code in the User mode most of the time.
APPENDIX D. RABBIT 3000A INTERNAL I/O REGISTERS Table D-1 provides a list of all the Rabbit 3000A internal I/O registers. Table D-1.
Table D-1.
Table D-1.
Table D-1.
Table D-1.
Table D-1.
Table D-1.
334 Rabbit 3000 Microprocessor
NOTICE TO USERS RABBIT SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE-SUPPORT DEVICES OR SYSTEMS UNLESS A SPECIFIC WRITTEN AGREEMENT REGARDING SUCH INTENDED USE IS ENTERED INTO BETWEEN THE CUSTOMER AND RABBIT SEMICONDUCTOR PRIOR TO USE.
INDEX Numerics D G 5 V tolerant inputs ................ 11 design features ........................ 9 5 V tolerant inputs ............. 11 BIOS ................................. 19 clock spectrum spreader .... 18 cold boot ........................... 52 input capture channels ...... 16 instruction set ...................... 9 interrupt priorities ............... 9 memory support .................. 9 parallel I/O ........................ 13 PWM outputs .................... 17 quadrature encoder inputs .
M memory A16, A19 inversions (/CS1 enable) .........................121 access time .......................215 access time delays ...........220 access times with clock doubler ........................221 allocation of extended code and data space .............123 breakpoint/debug controller ................................123 compiler operation ...........127 data and clock delays .......216 I and D space ...................125 I/O access time ................223 I/O read time delays ........
PDDDR ........................... 133 PDDR ...................... 133, 135 PDFR .............................. 133 PEBxR ............................ 138 PECR ...................... 138, 139 PEDDR ........................... 138 PEDR ...................... 138, 139 PEFR ............................... 138 PFCR ....................... 140, 141 PFDCR ............................ 140 PFDDR ............................ 140 PFDR .............................. 140 PFFR ............................... 140 PGCR ...
S secondary watchdog timer ..292 serial ports .....................11, 161 9th bit protocols ...............196 address registers ..............168 baud rates .........................163 breaks ..............................194 clocked serial ports (Ports A– D) ................................182 clocked serial timing .......185 control registers (Ports A–B) ......................................173 control registers (Ports C–D) ......................................174 control registers (Ports E–F) ......