Microprocessor User's Manual

User’s Manual 107
Table 7-19. Input Capture Control/Status Register
Input Capture Control/Status Register (ICCSR) (Address = 0x56)
Bit(s) Value Description
7:2
(read)
These status bits (but not the interrupt enable bits) are cleared by the read of this
register, as is the Input Capture Interrupt.
7 0 The Input Capture 2 Start condition has not occurred.
(read) 1 The Input Capture 2 Start condition has occurred.
7 0 The corresponding Input Capture 2 Start interrupt is disabled.
(write) 1 The corresponding Input Capture 2 Start interrupt is enabled.
6 0 The Input Capture 2 Stop condition has not occurred.
(read) 1 The Input Capture 2 Stop condition has occurred.
6 0 The corresponding Input Capture 2 Stop interrupt is disabled.
(write) 1 The corresponding Input Capture 2 Stop interrupt is enabled.
5 0 The Input Capture 1 Start condition has not occurred.
(read) 1 The Input Capture 1 Start condition has occurred.
5 0 The corresponding Input Capture 1 Start interrupt is disabled.
(write) 1 The corresponding Input Capture 1 Start interrupt is enabled.
4 0 The Input Capture 1 Stop condition has not occurred.
(read) 1 The Input Capture 1 Stop condition has occurred.
4 0 The corresponding Input Capture 1 Stop interrupt is disabled.
(write) 1 The corresponding Input Capture 1 Stop interrupt is enabled.
3 0 The Input Capture 2 counter has not rolled over to all zeros.
(read) 1 The Input Capture 2 counter has rolled over to all zeros.
3 0 No effect on Input Capture 2 counter. This bit always reads as zero.
(write) 1 Reset Input Capture 2 counter to all zeros and clears the rollover latch.
2 0 The Input Capture 1 counter has not rolled over to all zeros.
(read) 1 The Input Capture 1 counter has rolled over to all zeros.
2 0 No effect on Input Capture 1 counter. This bit always reads as zero.
(write) 1 Reset Input Capture 1 counter to all zeros and clears the rollover latch.
1:0 0x Normal Input Capture operation.
x0 Normal Input Capture operation.
11
Reserved for test. The Input Capture counter increments at both bit 0 and bit 8.
There is no carry from lower byte to higher byte.