Microprocessor User's Manual

User’s Manual 189
In HDLC mode the internal clock comes from the output of Timer A2. This timer output is
divided by sixteen to form the transmit clock, and is fed to the Digital Phase-Locked Loop
(DPLL) to form the receive clock. The DPLL is basically just a divide-by-16 counter that
uses the timing of the transitions on the receive data stream to adjust its count. The DPLL
adjust the count so that the output of the DPLL will be properly placed in the bit cells to
sample the receive data. To work properly, then, transitions are required in the receive data
stream. NRZ data encoding does not guarantee transitions in all cases (a long string of
zeros for example), but the other data encodings do. NRZI guarantees transitions because
of the inserted zeros, and the Biphase encodings all have at least one transition per bit cell.
The DPLL counter normally counts by sixteen, but if a transition occurs earlier or later
than expected the count will be modified during the next count cycle. If the transition
occurs earlier than expected, it means that the bit cell boundaries are early with respect to
the DPLL-tracked bit cell boundaries, so the count is shortened, either by one or two
counts. If the transition occurs later than expected, it means that the bit cell boundaries are
late with respect to the DPLL-tracked bit cell boundaries, so the count is lengthened,
either by one or two counts. The decision to adjust by one or by two depends on how far
off the DPLL-tracked bit cell boundaries are. This tracking allows for minor differences in
the transmit and receive clock frequencies.
With NRZ and NRZI data encoding, the DPLL counter runs continuously, and adjusts
after every receive data transition. Since NRZ encoding does not guarantee a minimum
density of transitions, the difference between the sending data rate and the DPLL output
Serial Clock
Biphase-Space
Biphase-Mark
NRZ Data
NRZI
Biphase-Level
NRZI
Biphase-Space
Biphase-Mark
data "1" "1" "1" "1""0" "0""0""0"