User Guide

You can reserve this area of system memory for ISA adapter ROM. When this area is reserved, it

cannot be cached. The user information of peripherals that need to use this area of system memory

usually discusses their memory requirements. The settings are: Enabled and Disabled.

CPU Latency Timer

During Enabled, A deferrable CPU cycle will only be Deferred after it has been in a Snoop Stall for

31 clocks and another ADS# has arrived. During Disabled, A deferrable CPU cycle will be Deferred

immediately after the GMCH receives another ADS#.

Delayed Transaction

The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles. Select

Enabled to support compliance with PCI specification version 2.1. The settings are: Enabled and

Disabled.

On-Chip Video Window Size

This option enabled/disabled the on-chip video windows size for VGA driver use. The settings are:

enabled, Disabled.

AGP Graphics Aperture Size

This option determines the effective size of the graphics aperture used in the particular PAC

configuration. The AGP aperture is memory-mapped, while graphics data structure can reside in a

graphics aperture. The aperture range should be programmed as not cacheable in the processor cache,

accesses with the aperture range are forwarded to the main memory, then PAC will translate the

original issued address via a translation table that is maintained on the main memory. The option

allows the selection of an aperture size of 32MB, 64MB.

3-6-1 SDRAM Timing Setting

SDRAM Timing Setting

Item Help

SDRAM CAS Latency Time 3

SDRAM Cycle Time Tras/Trc 6/8

SDRAM RAS-to-CAS Delay 3

SDRAM RAS Precharge Time 3

DRAM CTL Buffer strengths Normal

DRAM MD Buffer strengths Normal

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SDRAM CAS Latency Time

When synchronous DRAM is installed, the number of clock cycles of CAS latency depends on the

DRAM timing. The settings are: 2 and 3.

SDRAM Cycle Time Tras/Trc

Select the number of SCLKs for an access cycle. The settings are: 5/7 and 6/8.