User's Manual

DOC No: ZB7412-00A-DTS-R03
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Copyright © JORJIN TECHNOLOGIES INC. 2017 26
http://WWW.JORJIN.COM.TW
TA = 25°C, VDDS = 3.8 V
GPIO pullup current
Input mode, pullup enabled, Vpad = 0 V
277
μA
GPIO pulldown current
Input mode, pulldown enabled, Vpad = VDDS
113
μA
GPIO high/low input
transition, no hysteresis
IH = 0, transition between reading 0 and reading 1
1.67
V
GPIO low-to-high input
transition, with hysteresis
IH = 1, transition voltage for input read as 0→1
1.94
V
GPIO high-to-low input
transition, with hysteresis
IH = 1, transition voltage for input read as 1→0
1.54
V
GPIO input hysteresis
IH = 1, difference between 0→1 and 1→0 points
0.4
V
TA = 25°C
VIH
Lowest GPIO input voltage reliably interpreted as a
”High”
0.8
VDDS
VIL
Highest GPIO input voltage reliably interpreted as
a ”Low”
0.2
VDDS
4.25. Timing Requirements
Min
Typ
Max
Units
Rising supply-voltage slew rate
0
100
mV/μs
Falling supply-voltage slew rate
0
20
mV/μs
Falling supply-voltage slew rate, with low-power flash settings
(1)
3
mV/μs
Positive temperature
gradient in standby
(2)
No limitation for negative temperature
gradient, or outside standby mode
5
°C/s
CONTROL INPUT AC CHARACTERISTICS
(3)
RESET_N low duration
1
μs
SYNCHRONOUS SERIAL INTERFACE (SSI)
(4)
S1 (SLAVE)
(5)
T
clk_per
SSIClk period
12
65024
system clock
S2
(5)
t
clk_high
SSIClk high time
0.5
T
clk_per
S3
(5)
t
clk_low
SSIClk low time
0.5
T
clk_per
(1) For smaller coin cell batteries, with high worst-case end-of-life equivalent source resistance, a 22-μF VDD input
capacitor must be used to ensure compliance with this slew rate.
(2) Applications using RCOSC_LF as sleep timer must also consider the drift in frequency caused by a change in
temperature.
(3) T
A
= –40°C to 85°C, VDDS = 1.8 V to 3.8 V, unless otherwise noted.
(4) T
c
= 25°C, V
DDS
= 3.0 V, unless otherwise noted. Device operating as SLAVE. For SSI MASTER operation, see Section