User's Manual

DOC No: ZB7412-00A-DTS-R03
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Copyright © JORJIN TECHNOLOGIES INC. 2017 34
http://WWW.JORJIN.COM.TW
5.2. Reference Schematic
J1
HEADER 5x2/SM
2
4
6
8
10
1
3
5
7
9
nRESET
JTAG_TCK
JTAG_TMS
VDDS
DIO_2
DIO_1
DIO_0
JTAG_TCK
JTAG_TMS
DIO_4
DIO_3
DIO_6/
DIO_5
DIO_7nRESET
DIO_9
DIO_8
DIO_13
DIO_12
DIO_11
DIO_10
DIO_14
cJTAG Interface
VDDS
R6
100K
RES0402
VDDS
G1 G2
G3 G4
U1
ZB7
DIO_0
4
DIO_1
5
JTAG_TMSC
9
JTAG_TCKC
10
DIO_5
11
DIO_6
12
RESET_N
13
DIO_7
14
DIO_8
15
DIO_9
16
DIO_10
17
DIO_11
18
DIO_12
19
DIO_13
20
DIO_14
21
VDDS
22
GND1
G1
GND2
G2
GND3
G3
GND4
G4
DIO_4
8
DIO_3
7
DIO_2
6
GND
3
GND5
1
NC
2
VDDS2
23
NC
24
GND6
25
 No external decoupling is required.
 The reset line should have an external pullup resistor unless the line is actively driven.
Placement of this component is not critical.
 All Digital Peripheral Pins can be routed to any GPIO.