Data Sheet

Doc No: WG7833-B0-DTS-R06
Copyright © JORJIN TECHNOLOGIES INC. 2018
http://www.jorjin.com.tw
CONFIDENTIAL
Page 14
4.1.3. External Slow Clock Input (SLOW_CLK)
The supported digital slow clock is 32.768 kHz digital (square wave).
Parameter
Condition
Sym
Min.
Typ.
Max.
Units
Input slow clock Frequency
32.768
KHz
Input slow clock accuracy
(Initial + temp + aging)
WLAN, BT
+/-250
ppm
Input Transition time Tr/Tf
- 10% to 90%
Tr/Tf
100
ns
Frequency input duty Cycle
15
50
85
%
Input Voltage Limits
Square Wave,
DC-coupled
Vih
0.65xVIO
VIO
Vpeak
Vil
0
0.35xVIO
Input Impedance
1
MΩ
Input Capacitance
5
pF
4.1.4. External Fast Clock Requirements (-40 to +85°C)
Parameter
Condition
Min.
Typ.
Max.
Unit
Frequency
26
MHz
Frequency Accuracy
Short term (voltage and temp. effect)
± 20
ppm
Long term (including aging)
± 20
Input voltage limits
(TCXO_CLK_IN)
Sine wave/ clipped sine wave,
ac-coupled
2.4GHz WLAN
0.2
1.4
Vp-p
5GHz WLAN
0.8
1.4
Input impedance
Input resistance
20
KΩ
Input capacitance
2.5
pF
Power-up time
(1)
5
ms
Phase noise 2.4GHz
for 26MHz, 20MHz
SISO
Measured at 1 KHz offset
-123.4
dBc/Hz
Measured at 10 KHz offset
-133.4
dBc/Hz
Measured at 100 KHz offset
-138.4
dBc/Hz
Phase noise 2.4GHz
for 26MHz, 40MHz
SISO
Measured at 1 KHz offset
-128.4
dBc/Hz
Measured at 10 KHz offset
-135.4
dBc/Hz
Measured at 100 KHz offset
-139.9
dBc/Hz
Phase noise 5GHz for
26MHz, 20/40 MHz
SISO
Measured at 1 KHz offset
-128.4
dBc/Hz
Measured at 10 KHz offset
-145.4
dBc/Hz
Measured at 100 KHz offset
-148.4
dBc/Hz
(1) Power-up time is calculated from the time CLK_REQ_OUT asserted till the time the TCXO_CLK amplitude is within
voltage limit specified above and TCXO_CLK frequency is within 0.1 ppm of final steady state frequency.