Data Sheet

Doc No: WG7833-B0-DTS-R06
Copyright © JORJIN TECHNOLOGIES INC. 2018
http://www.jorjin.com.tw
CONFIDENTIAL
Page 36
7. REFERENCE SCHEMATIC
BT_EN_1V8
R3 0R RES1005
VIO_IN
WLAN_I RQ_1V8
R1
NL_10K
RES1005
TCXO_CLK_IN
C4
1uF
CAP1005
For RTTT test
VBAT_IN
EXT_32K
TCXO1
TCXO/2016/26MHz
TCXO-2.0X1.6
GND
1
VCC
4
OUT
3
GND
2
C1
33pF
CAP1005
U1
WG7833_03_31_01-B0 D01 Module
E-12X12.8-0.6-TOP
GND
C13
GND
C14
GND
C15
GND
C16
NL
B16
NL
B15
NL
B14
NL
B13
NL
B12
NL
B11
NL
B10
NL
B9
NL
B8
NL
B7
GP1O12
B6
GPIO10
B5
GPIO9
B4
GPIO11
B3
NL
J9
NL
J8
NL
B2
NL
B1
CLK_REQ_OU T
J10
NL
J13
NL
J7
NL
J6
NL
J5
NL
J4
GND
J11
GND
J12
GND
J3
VBAT_IN
D2
GND
J1
GND
A1
WL_SDI O_D3
A2
WL_SDI O_CMD
A3
WL_SDI O_D2
A4
WL_SDI O_D0
A5
WL_SDI O_D1
A6
WL_SDI O_CLK
A7
GND
A8
BT_HC I_RX
A12
BT_HC I_RTS
A10
BT_HC I_CTS
A9
NL
A15
GND
A16
NL
A17
GND
A18
BT_AUD_FSY NC
K13
BT_AUD_CLK
K12
BT_AUD_IN
K11
GND
K10
SLOW_CLK
K9
GND
K8
GND
K3
GND
K6
BT_AUD_OUT
K7
GND
K4
GND
K5
RF_ANT_BG
K2
GND
K1
GND
D20
GND
D15
NL
D5
GND
D6
PA_DC2D C_OUT
D9
GND
D8
NL
D14
GPIO_4
D10
BT_EN
D12
GND
J2
RF_ANT_A
D19
GND
D16
GND
D17
GND
D18
GND
C12
WLAN_I RQ
C11
WLAN_EN
C10
TCXO_CLK_IN
C9
NL
C8
GPIO3_WL_U ART_DBG
C6
NL
D7
NL
C5
BT_UAR T_DEBUG
C4
NL
C3
NL
C2
GND
C1
GND
E1
GND
E2
GND
E3
GND
E4
GND
F4
GND
F3
NL
A13
NL
A14
NL
D13
GPIO_2/W L_RS232_RX
D11
NL
D4
NL
D3
GPIO1/W L_232_TX
C7
GND
D1
GND
F2
GND
F1
VIO_IN
A19
GND
A20
BT_HC I_TX
A11
WL/BT_2.4G ANT
L3
NL
IND 1005
C11
10pF
CAP1005
C10
NL_10pF
CAP1005
C12
10pF
CAP1005
Reserved for RF test.
Closed to Module.
L4
NL
IND 1005
Pi-Circuit for Antenna matching.
ANT2
1
2
CLK_REQ_OU T_1833
TP9
1
WL_RS232_TX
VDD_TCXO_OUT
U2
SOT-23-5
TPS73618DBV
IN
1
GND
2
EN
3
NR/FB
4
OUT
5
C18
0.1uF
CAP1005
C19
10uF
CAP2012
C20
0.1uF
CAP1005
C22
10nF
CAP1005
VBAT_IN
WL_5G ANT (For WG7833/03 Only)
L1
NL
IND 1005
C5
NL_10pF
CAP1005 C3
10pF
CAP1005
Reserved for RF test.
Closed to Module.
C6
10pF
CAP1005
L2
NL
IND 1005
VDD_TCXO_OUT
ANT1
1
2
Pi-Circuit for Antenna matching.
CLK_REQ_OU T_1833
R22 0R RES1005
R19 0R RES1005
For BT (WG7833/31)
BD_HC I_TX_1V8
BD_HC I_RX_1V8
BD_HC I_CTS_1V8
R21 0R RES1005
R20 0R RES1005
R7 0R RES1005
BT_PCM_AUD_IN
BT_PCM_AUD_CLK
R8 0R RES1005
R10 0R RES1005
BT_PCM_AUD_FSY NC
Must reserve PU cricuit
for Debug.
C2
0.1uF
CAP1005
BT_PCM_AUD_OUT
R4 0R RES1005
C16
0.1uF
CAP1005
OSC1
OSC/3225/ 32.768kHz
EN
1
VCC
4
OUT
3
GND
2
R9
0R
RES1005
32.768KHz source select
VIO_IN
TP3
1
50 ohms single ended
ANTENNA CIRCUITS
TP4
1
WL_RS232_R X
J2
U.F L-R-SMT-1(10)
U.FL
1
2
3
HOST_SLOWCLK_1V8
R5
0R
RES1005
C17
0.1uF
CAP1005
VIO_IN
WL_EN_1V8
R2 0R
RES1005
For BT (WG7833/31)
R11 0R RES1005
R15 0R RES1005
R12 0R RES1005
R18 0R RES1005
R14 0R RES1005
SDIO_D 3_1V8
R16 0R RES1005
SDIO_C LK_1V8
SDIO_D 0_1V8
SDIO_D 2_1V8
SDIO_C MD_1V8
SDIO_D 1_1V8
For BT (WG7833/31)
TP1
1
TP2
1
For Logger
J1
U.F L-R-SMT-1(10)
U.FL
1
2
3
BD_HC I_RTS_1V8
C9
NL
CAP1005
C13
NL
CAP1005
C7
NL
CAP1005
C8
NL
CAP1005
C15
NL
CAP1005
C14
NL
CAP1005
** The six traces from Module to Host must be
treated like a bus. The bus length shall be as short
as possible and every trace length must be the same as
the others. Enough space above 2 time trace width or
ground shielding between trace and trace will be benefit
to make sure signal quality, especially for SDIO_CLK
trace. Besides, please remember to keep them away from
the other digital or analog signal traces. To add ground
shielding to around the buses will be helpful.
** It's recommended to reserve SDID matching circuits
and keep them close to module for signal optimization
WiFi SDIO Matching Circuit
SDIO_D1_1V8
SDIO_CLK_1V8
SDIO_D3_1V8
SDIO_D2_1V8
** All test point must reserved for test
SDIO_CMD_1V8
SDIO_D0_1V8
In green circle is a necessary part
** SDIO lines should be held high by the host
Boot Conditions
Scheme Brief
WiFi Interface: SDIO
Slow Clock: 32.768KHz for module boot
and deep sleep
VIO_IN: 1.62~1.95V => 1.8V TYP
VBAT_IN: 2.9~4.8V => 3.7V TYP
Fast Clock:
External TCXO 26MHz
Slow Clock: 32.768KHz
Figure 7-1 Module Reference Schematic