Projector Service Manual
Table Of Contents
- DECLARATION OF CONFORMITY
- BZSAFE.PDF
- CH1INTRO.PDF
- CH2SYSDE.PDF
- Functional Descriptions
- Contents
- Cover and Base
- External Power Requirements
- Electronics Systems Overview
- System Power
- Card Cage
- Circuit Boards
- Raster Timing Generator Board (RTG) p/n 100568
- Sync Generator
- Sync Detector and Selector
- Serration and Equalization Lockout
- Phase Locked Loop
- VSYNC Detector, Field Separator, and Mux
- Adjustment Counters
- Serial Communication
- Raster Timing Generator I/O
- Interlocks and Protection
- Horizontal Deflection Board P/N 102523 (HDB)
- Vertical Oscillator
- Horizontal Phase Locked Loop
- Horizontal Centering
- Horizontal Power Supply
- Flyback Switching
- Geometric Correction
- Output Section
- Horizontal Sweep Failure Detection
- Serial Communication
- Horizontal Deflection Board I/O
- Interlocks and Protection
- Vertical Deflection Board P/N 102521(VDB)
- Vertical Preamps
- Vertical Amplifiers
- Sweep Failure Detection
- Side Pincushion and Keystone Correction
- Horizontal Linearity Correction
- Top and Bottom Pincushion and Keystone Correction
- Correction Amplifiers
- Serial Communication
- General I/O
- Interlocks and Shutdowns
- Video Processor Board P/N 104672 (VPB)
- Decoder
- Video/Sync Mux
- V & H Sync Strip
- SG Sync Strip
- B, G, and R Brightness and Contrast Amplifiers
- On-Screen Switch
- Gamma Correction
- Switch Logic and Video Enable
- RGB Sensitivity and Threshold Amplifier
- ILA® Bias
- Dynamic Focus Amplifier
- Serial Communication
- General I/O
- Interlocks and Protection
- Video Amplifier Board P/N 103567 or 103774 (VAB)
- Video Signal
- Failure Detection
- Beam Current Sense
- DC Restore
- Arc Protection
- Blanking
- Enable Circuit
- Focus
- Filament Supply
- General I/O
- System Controller Board P/N 104668 (SCB)
- General Functional Description
- CPU
- Working and Compressed Memory
- Expanded Memory
- Correction Address Generator
- DACs
- DSP
- Overlay Memory
- Overlay Address Generator
- Overlay Interface
- LED Display Buffers and Logic
- RS232 Interface
- IR Interface
- IIC Interface
- Serial Interface
- General I/O
- Backplane Board p/n 100571
- Optical Section
- Image Light Amplifier
- Functional Descriptions
- CH3ADJST.PDF
- CH4MAINT.PDF
- Maintenance Remove/Replace)
- Contents
- Introduction
- Projector Covers
- Ventilation Filters
- Arc Lamp Assembly
- System Power Supply
- Electronics Module
- Cathode Ray Tube (CRT)
- Video Amplifier Board (VAB)
- CRT Yoke
- High Voltage Power Supply (HVPS)
- Card Cage (Printed Circuit Boards)
- Image Light Amplifier Assembly
- Projection Lens
- (SCB) Socket Battery Replacement
- Recommended Spares
- Maintenance Remove/Replace)
- CH5TRBSH.PDF
- HGLOSS.PDF
Chapter 2—Functional Description
Model 330, 340SC and 370SC Service Manual 2-21
shaped to be three (3) horizontal periods in length. This signal, /VSYNCSC (pulse-
shaped vertical sync) is then sent to the SCB and the VPB.
Adjustment Counters
The adjustment counters implement the following timing functions:
Left side, right side, top side, and bottom side blanking.
Vertical and horizontal timing for convergence correction and overlay.
Pincushion and linearity correction timing.
Vertical phase.
DC restore timing.
The four-(4) sides' blanking adjustments are accomplished by counting from the
regenerated H and VSYNC signals respectively. Each adjustment is independent of the
others. Vertical blanking is accomplished by counting a specified number of horizontal
lines after the vertical sync signal out of the VSYNC Mux. The top blanking counts the
commanded number of lines then unblanks the picture. The bottom blanking counts the
commanded number of lines then blanks the image.
Horizontal blanking is accomplished by counting a specified number of Hx224 clock
pulses after the regenerated HSYNC pulse, /HSYNCR). The left side blanking counts the
commanded number of clock pulses then unblanks the image. The right blanking counts
the commanded number of clock pulses then blanks the image. The outputs from these
counters are combined with a signal indicating PLL lock, into a composite blanking
signal VIDBLANK (high when the image is to be blanked) that is sent to the VPB. The
user selects the actual position of the four sides' blanking by adjusting from the remote
control.
The SCB calculates the number of clock pulses to count for each of the four sides based
on the input from the user, and sends those numbers to the appropriate counters via the
IIC serial communication bus signals LBlank, RBlank, TBlank, and BBlank.
Adjustment counters also generate the convergence correction and overlay address
generators’ timing signals. The correction bit-map address counter's MAPST (timing
pulse to tell the correction and overlay address generators to start a new frame) timing
pulse is generated by counting the commanded number of /HSYNCR pulses since the
vertical deflection flyback start pulse. The /CORSTRT (signal that indicates to the SCB
when to start the correction and overlay address generators counting) timing signal is a
pulse signal sent to the SCB. Its timing is determined by counting the commanded
number of Hx224 pulses after the /HSYNCR signal.
The position of the overlays (including menus and test patterns) and correction maps is
controlled automatically in the vertical direction. In the horizontal direction, the user
controls the position via the MENU POSITION selection under the TIMING SETUP
MENU. This circuit also determines the phase between the regenerated HSYNC and the
HV Flyback from Deflection. This value is read by the SCB over the IIC bus.
The pincushion and linearity correction timing signal is a pulse signal called /PCST that
is sent to the Vertical Deflection Board. The signal is generated using the same timing