Projector Service Manual
Table Of Contents
- DECLARATION OF CONFORMITY
- BZSAFE.PDF
- CH1INTRO.PDF
- CH2SYSDE.PDF
- Functional Descriptions
- Contents
- Cover and Base
- External Power Requirements
- Electronics Systems Overview
- System Power
- Card Cage
- Circuit Boards
- Raster Timing Generator Board (RTG) p/n 100568
- Sync Generator
- Sync Detector and Selector
- Serration and Equalization Lockout
- Phase Locked Loop
- VSYNC Detector, Field Separator, and Mux
- Adjustment Counters
- Serial Communication
- Raster Timing Generator I/O
- Interlocks and Protection
- Horizontal Deflection Board P/N 102523 (HDB)
- Vertical Oscillator
- Horizontal Phase Locked Loop
- Horizontal Centering
- Horizontal Power Supply
- Flyback Switching
- Geometric Correction
- Output Section
- Horizontal Sweep Failure Detection
- Serial Communication
- Horizontal Deflection Board I/O
- Interlocks and Protection
- Vertical Deflection Board P/N 102521(VDB)
- Vertical Preamps
- Vertical Amplifiers
- Sweep Failure Detection
- Side Pincushion and Keystone Correction
- Horizontal Linearity Correction
- Top and Bottom Pincushion and Keystone Correction
- Correction Amplifiers
- Serial Communication
- General I/O
- Interlocks and Shutdowns
- Video Processor Board P/N 104672 (VPB)
- Decoder
- Video/Sync Mux
- V & H Sync Strip
- SG Sync Strip
- B, G, and R Brightness and Contrast Amplifiers
- On-Screen Switch
- Gamma Correction
- Switch Logic and Video Enable
- RGB Sensitivity and Threshold Amplifier
- ILA® Bias
- Dynamic Focus Amplifier
- Serial Communication
- General I/O
- Interlocks and Protection
- Video Amplifier Board P/N 103567 or 103774 (VAB)
- Video Signal
- Failure Detection
- Beam Current Sense
- DC Restore
- Arc Protection
- Blanking
- Enable Circuit
- Focus
- Filament Supply
- General I/O
- System Controller Board P/N 104668 (SCB)
- General Functional Description
- CPU
- Working and Compressed Memory
- Expanded Memory
- Correction Address Generator
- DACs
- DSP
- Overlay Memory
- Overlay Address Generator
- Overlay Interface
- LED Display Buffers and Logic
- RS232 Interface
- IR Interface
- IIC Interface
- Serial Interface
- General I/O
- Backplane Board p/n 100571
- Optical Section
- Image Light Amplifier
- Functional Descriptions
- CH3ADJST.PDF
- CH4MAINT.PDF
- Maintenance Remove/Replace)
- Contents
- Introduction
- Projector Covers
- Ventilation Filters
- Arc Lamp Assembly
- System Power Supply
- Electronics Module
- Cathode Ray Tube (CRT)
- Video Amplifier Board (VAB)
- CRT Yoke
- High Voltage Power Supply (HVPS)
- Card Cage (Printed Circuit Boards)
- Image Light Amplifier Assembly
- Projection Lens
- (SCB) Socket Battery Replacement
- Recommended Spares
- Maintenance Remove/Replace)
- CH5TRBSH.PDF
- HGLOSS.PDF
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Chapter 2—Functional Descriptions
2-22 Model 330. 340SC, and 370SC Service Manual
method as the /CORSTRT signal but has a separate command from the SCB. It controls
the timing of the top and bottom pincushion correction, top and bottom keystone
correction, and horizontal linearity correction. The signal timing is selected by the user
and controlled by the SCB. Adjusting P
INCUSHION
P
OSN
under the T
IMING
S
ETUP
M
ENU
controls it.
Vertical phase adjustment is accomplished by timing the /VFBST (vertical start) signal
with respect to the regenerated vertical sync signal. This signal is generated by counting a
commanded number of horizontal lines after the vertical sync signal /VSYNCSC. The
signal timing is selected by the user and controlled by the SCB. It is controlled by
adjusting PHASE using the up/down arrows.
DC restore timing determines the point in time that the signal is clamped and the DC
restore (Section 2.6.4, Video Processor Board) function is accomplished. The user has
three (3) choices from which the DC restore timing can be selected. These are Backporch
(BP), Tri-level (TL), and Sync-tip (ST). The choices are selected in the SL column of the
C
HANNEL
L
IST
under the C
HANNEL
M
ENU
(Figure 5-1, Menu Structure).
The DC restore timing counts a preset number of Hx224 clock pulses after the HSYNC
signal leading edge. ST will clamp and DC restore during the time that the HSYNC pulse
is active. ST clamping is timed with respect to the leading edge of the HSYNC pulse. It is
seldom used but is necessary when there is no back porch to clamp on (image starts
immediately after the sync pulse). BP will clamp and DC restore shortly after the HSYNC
pulse. BP clamping is timed with respect to the trailing edge of the HSYNC pulse. The
timing is calculated to be on the back porch of the signal (after the sync pulse but before
the image begins). This is the most frequently used clamp timing.
The default setting for the DC restore timing is BP when a new channel is set up. TL
clamping occurs significantly after the HSYNC pulse. The purpose of TL timing is to
provide DC restore timing that is compatible with the Tri-level type sync used with
HDTV signals. Like BP, TL clamping is timed with respect to the trailing edge of the
HSYNC pulse. The output of the Synctip/Backporch circuit is a pulse signal (DCRSTR)
going to the VPB.
Serial Communication
The RTG uses only the IIC bus for serial communication with the SCB (Section 2.6.6).
The information transferred over the IIC bus is indicated below (I = input to RTG, O =
output from RTG). A change in output data generates an interrupt pulse.
Table 2-4
IIC BUS Information
I/O
Information
Description
I
Priority Select
Commanded sync selection priority
(always fixed as described above).
I
Vertical Flyback Start Delay
Commanded V phase.
I
Map Start Delay
Commanded timing for vertical positioning
of correction map.
I
L Blank
Commanded position of left blanking.
I
R Blank
Commanded position of right blanking.