KS152JB Universal Communications Controller Technical Specifications 1.0 INTRODUCTION The 80C152 Universal Communications Controller is an 8-bit microcontroller designed for the intelligent management of peripheral systems or components. The 80C152 is a derivative of the 80C51 and retains the same functionality.
Kawasaki LSI USA, Inc. Page 2 of 120 XTAL2 XTAL1 RST ALE EA PSEN P1.0 - P1.7 PORT1 DRIVERS PORT1 LATCH OSCILLATOR INSTRUCTTIMING ION AND CONTROL REGISTER B REGISTER RAM ADDRESS REGISTER PRBS MYSLOT TSTAT SLOTTM P3.0 - P3.
KS152JB Universal Communications Controller Technical Specifications 2.1 Pin Description Table 1: PIN DESCRIPTION Name Description Port 0 Port 0 is an 8-bit open drain bi-directional I/O Port. As an output port each pin can sink 8 LS TTL inputs. Port 0 pins that have 1s written to them float, and in that state can be used as high-impedance inputs. external program memory if EBEN is pulled low.
KS152JB Universal Communications Controller Technical Specifications Table 1: PIN DESCRIPTION Port 3 Port 3 is an 8-bit bi-directional I/O port with internal pullups. Port 3 pins that have 1s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL, on the data sheet) because of the pullups.
KS152JB Universal Communications Controller Technical Specifications Table 1: PIN DESCRIPTION ALE Address Latch Enable output signal for latching the low byte of the address during accesses to external memory. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. While in Reset, ALE remains at a constant high level.
KS152JB Universal Communications Controller Technical Specifications 2.2 Special function Registers The following table lists the SFR’s present in 80152. Note that not all the addresses are occupied by SFR’s. The unoccupied addresses are not implemented and should not be used by the customer.
KS152JB Universal Communications Controller Technical Specifications between the RST pin being pulled low and the internal reset being generated. During this time the CPU continues its normal operations. The internal reset signal clears the SFRs except the port SFRs which have FFh written into them and the Stack Pointer which has 07h written to it. The SBUF is however in an indeterminate state. The Program Counter is reset to 0000h.
KS152JB Universal Communications Controller Technical Specifications Table 3: Reset Values of the SFRs SFR Name Reset Value SFR Name Reset Value IP XXX00000B SCON 00H IE 0XX00000B SBUF INDETERMINATE TMOD 00H PCON 0XXX0000B TCON 00H DARL0-1 INDETERMINATE DCON0-1 00H DARh0-1 INDETERMINATE GMOD X0000000B IFS 00H IEN1 XX000000B MYSLOT 00H IPN1 XX000000B PRBS 00H TCDCNT INDETERMINATE TCON 00H TFIFO INDETERMINATE TSTAT XX000100B 2.
KS152JB Universal Communications Controller Technical Specifications ADDR/DATA IDNAMX ADDRESS IDNAHI VCC VCC Internal Pullup P2.X Pin P0.X Pin 1 1 MUX PORT0OP MUX Q PORT2OP 0 Q 0 PORT2IP PORT0IP 3. Port 2 I/O Pad 1. Port 0 I/O Pad Alternate Output Function VCC Weak Internal Pullup VCC Weak Internal Pullup P1.X Pin P3.X Pin PORT1OP PORT3OP Alternate Output Function PORT3IP PORT1IP 2. Port 1 I/O Pad 4.
KS152JB Universal Communications Controller Technical Specifications Writing to a Port During the execution of an instruction that changes the value of a port SFR, the new value arrives at the port latch during S6P2. However, the port latch contents do not appear on the port pins till the next P1 phase. Therefore the new port data will appear on the port pins at S1P1 of the next machine cycle. Read-Modify-Write Feature Each port is split into its SFR and its corresponding I/O pad.
KS152JB Universal Communications Controller Technical Specifications Table 4: EA Program Fetch via PSEN EPSEN 0 0 P0, P2 Active Inactive 0 1 N/A N/A N/A 1 0 P5, P6 Inactive 1 1 P5, P6 P0, P2 Inactive Active EBEN Comments Addresses 0 - 0FFFFH Invalid Combination Addresses 0 - 0FFFFH Active Inactive Addresses 0 - 1FFFH Addresses 0 - 2000H 2.
KS152JB Universal Communications Controller Technical Specifications During External Memory Accesses, both Ports 0 and 2 are used for Address/ Data transfer and therefore cannot be used for general I/O purposes. During external program fetches, Port 2 uses strong pullups to emit 1s. 2.7 TIMER/COUNTERS This has two 16-bit Timer/Counters, TM0 andTM1. Each of these Timer/Counters has two 8 bit registers which form the 16 bit counting register.
KS152JB Universal Communications Controller Technical Specifications 7 TF1 6 TR1 5 TF0 4 TR0 3 2 1 0 IE1 IT1 IE0 IT0 TF1 Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when processor vectors to timer 1 interrupt routine. TR1 Timer 1 Run control bit. Set/Cleared by software to turn Timer/Counter on/off. TF0 Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when processor vectors to timer 0 interrupt routine.
KS152JB Universal Communications Controller Technical Specifications OSC S3P1 C/T I0 Tx pin Q I1 TLX THx 5 bits 8 bits TFx INTERRUPT TRx GATE INTx pin Timer/Counter in Mode 0 MODE 1 Mode 1 is similar to Mode 0 except that the counting register form a 16 bit counter, rather than a 13 bit counter. This means that all the bits of THx and TLx are used. .
KS152JB Universal Communications Controller Technical Specifications Mode 3 is used in cases where an extra 8 bit timer is needed. With Timer 0 in Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3. It can also be used as a baud rate generator for the serial port. C/T OSC S3P1 I0 T0 pin Q I1 TL0 5 bits TF0 INTERRUPT TH0 8 bits TF1 INTERRUPT TR0 GATE INT0 pin S3P1 TR1 Timer/Counter 0 in Mode 3 2.
KS152JB Universal Communications Controller Technical Specifications case of level triggered interrupt, the IE0 and IE1 flags are not cleared and will have to be cleared by the software. This is because in the level activated mode, it is the external requesting source that controls the interrupt flag bit rather than the on-chip hardware. The Timer 0 and 1 Interrupts are generated by the TF0 and TF1 flags. These flags are set by the overflow in the Timer 0 and Timer 1.
KS152JB Universal Communications Controller Technical Specifications 7 6 5 4 3 2 1 0 EGSTE EDMA1 EGSTV EDMA0 EGSRE EGSRV IEN1 (Additional interrupt enable register) (0C8H) Interrupt enable register for DMA and GSC interrupts. A 1 in any bit position enables that interrupt. IEN1.0 (EGSRV) - Enables the GSC valid receive interrupt. IEN1.1 (EGSRE) - Enables the GSC receive error interrupt. IEN1.2 (EDMA0) - Enables the DMA done interrupt for channel 0. IEN1.
KS152JB Universal Communications Controller Technical Specifications The interrupt flags are sampled in S5P2 of every machine cycle. In the next machine cycle, the sampled interrupts are polled and their priority is resolved. If certain conditions are met then the hardware will execute an internally generated LCALL instruction which will vector the process to the appropriate interrupt vector address. The conditions for generating the LCALL are 1.
KS152JB Universal Communications Controller Technical Specifications Table 5: Priority sequence Priority address Priority name Interrupt Symbolic name Interrupt Symbolic Name Vector Address 8 IPN1.4 PDMA1 IEN1.4 EDMA1 53H 9 IP.3 PT1 1E.3 ET1 1BH 10 IPN1.5 PGSTE IEN1.5 EGSTE 4BH 11 IP.4 PS IE.4 ES 23H Execution continues from the vectored address till an RETI instruction is executed.
KS152JB Universal Communications Controller Technical Specifications values are polled only in the next machine cycle. If a request is active and all three conditions are met, then the hardware generated LCALL is executed. This call itself takes two machine cycles to be completed. Thus there is a minimum time of three machine cycles between the interrupt flag being set and the interrupt service routine being executed. A longer response time should be anticipated if any of the three conditions are not met.
KS152JB Universal Communications Controller Technical Specifications 2.9 Power Down and Idle The processor has two Power Reduction modes, Idle and Power Down. Backup power is supplied through the VCC pin in these operations. The processor can be put into the Idle or the Power down mode by setting bits 0 or bit 1 respectively in the PCON SFR. Any instruction sets the PD bit in PCON SFR, causes that instruction to be the last instruction executed by the processor before going into the Power Down mode.
KS152JB Universal Communications Controller Technical Specifications 7 SMOD SMOD 6 -- 5 -- 4 -- 3 -- 2 -- 1 0 PD IDL Double Baud Rate bit. When cleared, the baud rate is halved, by dividing the serial clock by 2. -- Described later. PD Power Down bit. Setting this bit activates this mode. IDL Idle Mode bit. Setting this bit activates this mode. PCON: Power Control Register. There are two ways to terminate the Idle mode.
KS152JB Universal Communications Controller Technical Specifications The DMA circuitry stops operation in both Idle and power Down modes. Since operation is stopped in both modes, the process should be similar in each case. Specific steps that need to be taken include: notification to other devices that DMA operation is about to cease for a particular station or network, proper withdrawal from DMA operation, and saving the status of the DMA channels.
KS152JB Universal Communications Controller Technical Specifications Transmit Shift Register CLOCK 12 4 SM2 0 RxD P3.0 Alternate Output function SOUT Internal Data Bus 1 PARIN Write to SBUF LOAD CLOCK TX START TX SHIFT TX CLOCK TI SERIAL CONTROLLER Serial Interrupt RI RX CLOCK RI REN RX START SHIFT CLOCK LOAD SBUF RX SHIFT TxD P3.1 Alternate Output function CLOCK PAROUT RxD P3.
KS152JB Universal Communications Controller Technical Specifications Timer 1 Overflow Transmit Shift Register 2 Internal Data Bus SMOD 0 1 1 STOP 0 PARIN START Write to SBUF 16 LOAD CLOCK TX START TX SHIFT TX CLOCK TI SERIAL CONTROLLER 16 RX CLOCK 1-TO-0 DETECTOR RX START Serial Interrupt RI LOAD SBUF RX SHIFT CLOCK PAROUT RxD TxD SOUT BIT DETECTOR Internal Data Bus SBUF SIN D8 Receive Shift Register RB8 Read SBUF Serial Port Mode 1 Reception is enabled only if REN is high.
KS152JB Universal Communications Controller Technical Specifications If these conditions are met, then the stop bit goes to RB8, the 8 data bits go into SBUF and RI is set. Else the received frame may be lost. After the middle of the stop bit, the receiver goes back to looking for a 1-to-0 transition on the RxD pin. MODE 2 In this mode, 11 bits are transmitted on TXD and received on RXD.
KS152JB Universal Communications Controller Technical Specifications Clock / 2 Transmit Shift Register 2 SMOD 0 1 STOP SOUT D8 PARIN START 1 TB8 Internal Data Bus 0 Write to SBUF 16 LOAD CLOCK TX START TX SHIFT TX CLOCK TI SERIAL CONTROLLER 16 RX CLOCK 1-TO-0 DETECTOR RX START Serial Interrupt RI LOAD SBUF RX SHIFT CLOCK PAROUT RxD TxD BIT DETECTOR Internal Data Bus SBUF SIN D8 Receive Shift Register RB8 Read SBUF Local Serial Port Mode 2 MODE 3 This mode is similar to Mode 2 in a
KS152JB Universal Communications Controller Technical Specifications Timer 1 Overflow Transmit Shift Register 2 Internal Data Bus SMOD STOP SOUT D8 PARIN START 1 TB8 0 Write to SBUF 0 1 16 LOAD CLOCK TX START TX SHIFT TX CLOCK TI SERIAL CONTROLLER 16 1-TO-0 DETECTOR RX CLOCK RX START Serial Interrupt RI LOAD SBUF RX SHIFT CLOCK PAROUT RxD TxD BIT DETECTOR Internal Data Bus SBUF SIN D8 Receive Shift Register RB8 Read SBUF Local Serial Port Mode 3 Baud Rates In Mode 0 the baud rate i
KS152JB Universal Communications Controller Technical Specifications in auto-reload mode. In such a case the baud rate is given by Mode 1,3 baud rate = 2(SMOD - 5) X Oscillator Frequency / (12 x [256 - TH1]) It is also possible to achieve very low baud rates by putting Timer 1 in Mode1 as a 16 bit timer and enabling its interrupt. The Timer interrupt is used to reload the Timer 1 with a 16 bit value using software methods.
KS152JB Universal Communications Controller Technical Specifications 2.11 SINGLE-STEP OPERATION The processor does not have any pin which can directly force it to operate in the single-step mode. However the user can use the interrupt structure to obtain single-step operation. The user will be aware that the processor executes one more instruction after a RETI instruction and only then does it respond to an interrupt request.
lsn msn 0 1 2 3 4 5 6-7 8-F 0 nop ajmp ljmp rr a inc a inc d inc @ inc rn 1 jbc acall lcall rrc a dec a dec d dec @ dec rn 2 jb ajmp ret rl a add a, # add a, d add a, @ add a, rn 3 jnb acall reti rlc a addc a, # addc a, d addc a, @ addc a, rn 4 jc ajmp orl d, a orl d, # orl a, # orl a, d orl a, @ orl a, rn 5 jnc acall anl d, a anl d, # anl a, # anl a, d anl a, @ anl a, rn 6 jz ajmp xrl d, a xrl d, # xrl a, # xrl a, d xrl a, @ xrl a, rn
KS152JB Universal Communications Controller Technical Specifications 3.0 GLOBAL SERIAL CHANNEL 3.1 Introduction The Global Serial Channel (GSC) is a multi-protocol, high performance serial interface targeted for data rates up to 2 MBPS with on-chip clock recovery, and 2.4 MBPS using the external clock options. in applications using the serial channel, the GSC implements the Data Link Layer and Physical Link Layer as described in the ISO reference model for open systems interconnection.
KS152JB Universal Communications Controller Technical Specifications Table 9: Data N-Not available. M-Mandatory. O-Optional. P-Normally Preferred X-N/A Flags CRC Duplex h al f d u pl e x fu ll d u pl e x n o n e h ar d w ar e O M N O O O O O O O 1 O O O O 1 1 O O O 1 X 1 O O 1 1 1 X N O O O O N O O O O O Half Duples Full Duplex O O O O N O O Acknowledge: None Hardware User defined.
KS152JB Universal Communications Controller Technical Specifications Table 9: Data N-Not available. M-Mandatory. O-Optional.
KS152JB Universal Communications Controller Technical Specifications Table 10: preamble backoff Jam n o r m a l a lt e r n a t e d e t e r m i n i s ti c 8 3 n 2 o b n i b e t it b it N N N 1 1 O O O O O Half Duples Full Duplex O Acknowledge: None Hardware User defined. N-Not available. M-Mandatory. O-Optional.
KS152JB Universal Communications Controller Technical Specifications Table 10: preamble backoff Jam n o r m a l a lt e r n a t e d e t e r m i n i s ti c 8 3 n 2 o b n i b e t it b it Control cpu Control dma O O O O O O O O O Raw Receive O O Raw Transmit N CSMA SDLC N-Not available. M-Mandatory. O-Optional.
KS152JB Universal Communications Controller Technical Specifications be in some other mode than the user intends for a significant amount of time after reset. To prevent unwanted GSC errors from occurring, the user should not enable the GSC or the GSC interrupts for 170 machine cycles ((256 X 8) /12) after LNI bit is set. 3.2 CSMA/CD Operation 3.2.1 CSMA/CD OVERVIEW CSMA/CD Operates by sensing the transmission line for a carrier, which indicates link activity.
KS152JB Universal Communications Controller Technical Specifications PREAMBLE - The preamble is a series of alternating 1s and 0s. The length of the preamble is programmable to be 0, 8, 32, or 64 bits. The purpose of the preamble is to allow all the receivers to synchronize to the same clock edges and identifies to the other stations on-line that there is activity indicating the link is being used. For these reasons zero preamble length is not compatible with standard CSMA/CD, protocols.
KS152JB Universal Communications Controller Technical Specifications The CRC generator, as shown in figure below, operates by taking each bit as it is received and XOR’ing it with bit 31 of the current CRC. This result is then placed in temporary storage. The result of XOR’ing bit 31 with the received bit is then XOR’d with bits 0, 1,3,4,6,7,9,10,11,15,21,22,25 as the CRC is shifted right, the temporary storage space holding the result of XOR’ing bit 31 and the incoming bit is shifted into position 0.
KS152JB Universal Communications Controller Technical Specifications link remains high for 2 or more bit times. 3.2.3 INTERFRAME SPACE The interframe space is the amount of time that transmission is delayed after the link is sensed as being idle and is used to separate transmitted frames. In alternate back off mode, the interframe space may also be included in the determination of when retransmissions may actually begin. The C152 allows programmable interframe spaces of even numbers of times from 2 to 256.
KS152JB Universal Communications Controller Technical Specifications 3.2.4 CSMA/CD DATA ENCODING Manchester encoding/decoding is automatically selected when the user software selects CSMA/ CD transmission mode (See Figure below). In Manchester encoding the value of the bit is determined by the transition in the middle of the bit time, a positive transition is decoded as a 1 and a negative transition is decoded as a 0. The Address and Info bytes are transmitted LSB first. The CRC is transmitted MSB first.
KS152JB Universal Communications Controller Technical Specifications Narrow Pulses A valid Manchester waveform must stay high or low for at least a half bit-time, nominally 4 sample-times. Jitter tolerance allows a waveform which stays high or low for 3 sample-times to also be considered valid. A sample sequence which shows a second transition only 1 or 2 sample-times after the previous transition is considered to be the result of a collision.
KS152JB Universal Communications Controller Technical Specifications 3.2.6 RESOLUTION OF COLLISIONS How the GSC responds to a detected collision depends on what it was doing at the time the collision was detected. What it might be doing is either transmitting or receiving a frame, or it might be inactive.
KS152JB Universal Communications Controller Technical Specifications If a transmitting 8XC152 detects a collision during the preamble/BOF part of the frame that it is trying to transmit, it will complete the preamble/BOF and then begin the jam signal in the first bit time after BOF. If the collision is detected later in the frame., the jam signal will begin in the next bit time after the collision was detected.
KS152JB Universal Communications Controller Technical Specifications Random Backoff In either of the random algorithms, the first thing that happens after a collision is detected is that a I gets shifted into the TCDCNT (Transmit Collision Detect Count) register, from the right.
KS152JB Universal Communications Controller Technical Specifications BKOFF starts counting down from its preload value, counting slot times. At any time, the current value in BKOFF can be read by the CPU, but CPU writes to BKOFF have no effect. While BKOFF is counting down, if its current value is not 0, transmission is disabled. The output signal “BKOFF = 0” is asserted when BKOFF reaches 0, and is used to re-enable transmission.
KS152JB Universal Communications Controller Technical Specifications The highest slot assignment in the network is written by each station’s software into its TCDCNT register. Normal the highest slot assignment is just the total number of stations that are going to participate in the backoff algorithm. In deterministic backoff mode a collision will not cause a 1 to be shifted into TCDCNT. TCDCNT will still be ANDed with PRBS and the result loaded into BKOFF.
KS152JB Universal Communications Controller Technical Specifications interframe space and the preamble length such that the acknowledge is completed before IFS expires. This is normally done by programming IFS larger than the preamble. A transmitting station with HABEN enabled expects an acknowledge. It must receive one prior to the end of the interframe space, or else an error is assumed and the NOACK bit is set. Setting of the TDN bit is also delayed until the end of the interframe space.
KS152JB Universal Communications Controller Technical Specifications 3.3 SDLC Operation SDLC is a communication protocol developed by IBM and widely used in industry. It is based on a primary/ secondary architecture and requires that each secondary station have a unique address. The secondary stations can only communicate to the primary station, and then, only when the primary station allows communication to take place.
KS152JB Universal Communications Controller Technical Specifications number of address bits, but the automatic address recognition feature works on a maximum of 16bits. In SDLC the address are normally unique for each station. However, there are several classes of messages that are intended for more than one station. These messages are called broadcast and group addressed frames.
KS152JB Universal Communications Controller Technical Specifications that the correct remainder is left. The remainder that is checked for is 001110100001111B (1D0F Hex). If there is a mismatch, an error is generated. The user software has the option of enabling this interrupt so the CPU is notified. 16-Bit CRC 0 1 11 12 3 2 13 4 14 6 5 7 8 9 10 15 RECEIVED BIT EOF - The End Of Frame (EOF) indicates when the transmission is complete. The EOF is identified by the end flag.
KS152JB Universal Communications Controller Technical Specifications required for implementing bit stuffing and striping are incorporated into the GSC hardware. This makes the operation transparent to the user. About the only time this operation becomes apparent to the user, is if the actual data on the transmission medium is being monitored by a device that is not aware of the automatic insertion of 0s.
KS152JB Universal Communications Controller Technical Specifications count must be done by the user software. The Hardware Based Acknowledge option that is provided in the C152 is not compatible with standard SDLC protocol. 3.3.8 PRIMARY/SECONDARY STATIONS All SDLC networks are based upon a primary/secondary station relationship. There can be only one primary station in a network and all the other stations are considered secondary. All communication is between the primary and secondary station.
KS152JB Universal Communications Controller Technical Specifications 3.3.9 HDLC/SDLC COMPARISON HDLC (High level Data Link Control) is a standard adopted by the International Standards Organization (ISO). The HDLC standard is defined in the ISO document # ISO6159 -HDLC unbalanced classes of procedure. IBM developed the SDLC protocol as a subset of HDLC. SDLC confirms to HDLC protocol requirements, but is more restrictive. SDLC contains a more precise definition on the modes of operation.
KS152JB Universal Communications Controller Technical Specifications 3.5 USING THE GSC 3.5.1 LINE DISCIPLINE Line discipline is how the management of the transfer of data over the physical medium is controlled. Two types of line discipline will be discussed in this section: full duplex and half duplex. Full duplex is the simultaneous transmission and reception of data.Full duplex uses anywhere from two to four wires. At least one wire is needed for transmission and one write for reception.
KS152JB Universal Communications Controller Technical Specifications Some of the general areas that will impact the overall scheme on how to incorporate future changes to the system are: 1) Communication of the change to all the stations or the primary station. 2) Maximum distance for communication. This will affect the drivers used and the slot time. 3) More stations may be on the line at one time. This may impact the interframe space or the collision resolution used.
KS152JB Universal Communications Controller Technical Specifications registers. On the DMA channel servicing the receiver, the control register needs to be loaded as follows: DCONn.2 = 0, this sets the transfer mode so that response is to GSC interrupts and put the DMA control in alternate cycle mode; DCONn.3 = 1, this enables the demand mode; DCONn.4 = 0, this clears the automatic increment option for the source address; and DCONn.
KS152JB Universal Communications Controller Technical Specifications this same DMA bit. The interrupts EGSTE (IEN1.5), GSC transmit error; EGSTV (IEN1.3), GSC transmit valid; EGSRE (IEN1.1), GSC receive error; and EGSRV (IEN1.0), GSC receive valid; need to be enabled. The DMA interrupts are normally not used when servicing the GSC with the DMA channels. To ensure that the DMA interrupts are normally not used when servicing the GSC with the DMA channels.
KS152JB Universal Communications Controller Technical Specifications specified in the data sheet. For a description of the use of the GSC with external clock please read Section 3.5.11. 3.5.5 INITIALIZATION Initialization can be broken down into two major components, 1) initialization of the component so that its serial port is capable of proper communication; and 2) initialization of the system or a station so that intelligible communication can take place.
KS152JB Universal Communications Controller Technical Specifications inquiry for the address check, a timer is also started. If the timer expires before the inquiry is responded to, then that station assumes the address chosen is okay. In the second procedure, an initializing station asks for an address assignment from the system. This requires that some station on the link take care of the task of maintaining a record of which addresses are used. This station will be called station-1.
KS152JB Universal Communications Controller Technical Specifications age and currents that the GSC is capable of providing are the same levels as those for normal port operation. The signal used to enable the external drivers is DEN. No similar signal is needed for the receiver. DEN is active one bit time before transmission begins. In CSMA/CD DEN remains active for two bit times after the CRC is transmitted. In SDLC DEN remains active until the last bit of the EOF is transmitted. 3.5.
KS152JB Universal Communications Controller Technical Specifications LOCAL VALUE 0 1 1 1 0 0 MANCHESTER ENCODING “1” BIT TIME “1” BIT TIME (8 X BAUD) RECEIVE SAMPLING RATE RECEIVED DATA “1” BIT TIME “0” BIT TIME RECEIVED DATA 3.5.9 Transmit Waveforms The CSC is capable of three types of data encoding, Manchester, NRZI, and NRZ. Figure shows example of all three types of data encoding. BIT TIME 0 1 1 0 0 1 NRZ NRZI MANCHESTER Kawasaki LSI USA, Inc. Page 62 of 120 Ver. 0.
KS152JB Universal Communications Controller Technical Specifications 3.5.10 Receiver Clock Recovery The receiver is always monitored at eight times the baud rate frequency, except when an external clock is used. When using an external clock the receiver is loaded during the clock cycle. In CSMA/CD mode the receiver synchronizes to the transmitted data during the preamble. If a pulse is detected as being too short it is assumed to be noise or a collision.
KS152JB Universal Communications Controller Technical Specifications 3.5.11 External Clocking To select external clocking, the user is given three choices. External clocking can be used with the transmitter, with the receiver, or with both. To select external clocking for the transmitter, XTCLK (GMOD.7) has to be set to a 1. To select external clocking for the receiver, XRCLK (PCON.3) has to be set to a 1. Set ting both bits to 1 forces external clocking for the receiver and transmitter.
KS152JB Universal Communications Controller Technical Specifications to each station. When using 16-bit addressing, ADR0:ADR1 form one address and ADR2:ADR3 form the second address. If the receiver is enabled, it looks for a matching address after every BOF flag is detected. As the data is received, if the 8th (or 16th) bit does not match the address recognition circuitry, the rest of the frame is ignored and the search continues for another flag.
KS152JB Universal Communications Controller Technical Specifications and then writing to TFIFO. TEN must be set before loading the transmit FIFO, as setting TEN clears the transmit FIFO. TCDCNT should also be checked by user software and cleared if a collision occurred on a prior transmission. To enable the receiver, GREN (RSTAT.1) is set. After GREN is set, the GSC begins to look for a valid BOF.
KS152JB Universal Communications Controller Technical Specifications expected. When this type of collision occurs the GSC automatically handles the retransmission attempts for as many as eight tries. If on the eighth attempt a collision occurs, the transmitter is disabled, although the jam and back off are performed. If enabled, the CPU is then interrupted. The user software should then determine what action to take.
KS152JB Universal Communications Controller Technical Specifications would be one interframe space period after the line is sensed as being idle. As the number of stations approach 256 the probability of a successful transmission decreases rapidly. If there are more than 256 stations involved in the collision there would be no resolution since at least two of the stations will always have the same backoff interval selected.
KS152JB Universal Communications Controller Technical Specifications bits. Writing a one to a bit in AMSK0,1 masks out that corresponding bit in ADDR0,1. BAUD (94H) -GSC Baud Rate Generator - Contains the value of the programmable baud rate. The data rate will equal (frequency of the oscillator)/((BAUD +1) x (8)). Writing to BAUD actually stores the value in a reload register. The reload register contents are copied into the BAUD register when the Baud register decrements to 00H.
KS152JB Universal Communications Controller Technical Specifications can be masked in AMSK1:AMSK0. A received address of all ones will always be recognized in any mode. The user software is responsible for setting or clearing this flag. GMOD.5,6 (M0,M1) - Mode Select - Two test modes, an optional “alternate backoff” mode, or normal back-off can be enabled with these two bits. The user software is responsible for setting or clearing the mode bits.
KS152JB Universal Communications Controller Technical Specifications MYSLOT (0F5H) - Slot Address Register 4 6 2 5 3 7 DCJ DCR SA5 SA4 SA3 SA2 0 1 SA1 SA0 SAn = SLOT ADDRESS (BITS 5 - 0) MYSLOT.0, 1,2,3,4,5 - Slot Address -The six address bits choose 1 of 64 slot addresses. Address 63 has the highest priority and address 1 has lowest. A value of zero will prevent a station from transmitting during the collision resolution period by waiting until all the possible slot times have elapsed.
KS152JB Universal Communications Controller Technical Specifications PCON.3(XRCLK) -GSC External Receive Clock Enable- Writing a 1 to XRCLK enables an external clock to be applied to pin 5(Port 1.4). The external clock is used to determine when bits are loaded into the receiver. PCON.4 (GAREN) - GSC Auxiliary Receiver Enable Bit - This bit needs to be set to a 1 to enable the reception of back-to-back SDLC frames.
KS152JB Universal Communications Controller Technical Specifications data. The receive FIFO is a three byte buffer into which the receive data is loaded. A CPU read of the FIFO retrieves the oldest data and automatically updates the FIFO pointers. Setting GREN to a one will clear the receive FIFO. The status of this flag is controlled by the GSC. It is cleared if user empties receive FIFO. RSTAT.3 (RDN) - Receive Done - If set, indicates the successful completion of a receiver operation.
KS152JB Universal Communications Controller Technical Specifications TCDCNT (0D4H) - Transmit Collision Detect Count Contains the number of collisions that have occurred if probabilistic CSMA/CD is used. The user software must clear this register before transmitting a new frame so that the GSC backoff hardware can accurately distinguish a new frame from a retransmit attempt. In deterministic backoff mode, TCDCNT is used to hold the maximum number of slots.
KS152JB Universal Communications Controller Technical Specifications received, TDN is not set. An acknowledge is not expected following a broadcast or multi-cast packet. The status of this flag is controlled by the GSC. TSTAT.4(TCDT) - Transmit Collision Detect - If set, indicates that the transmitter halted due to a collision. It is set if a collision occurs during the data or CRC or if there are more than eight collisions. The status of this flag is controlled by the GSC. TSTAT.
KS152JB Universal Communications Controller Technical Specifications 4.0 DMA Operation The C152 contains DMA (Direct Memory Accessing) logic to perform high speed data transfers between any two of Internal Data RAM Internal SFRs External Data RAM In external RAM is involved, the Port 2 and Port 0 pins are used as the address/data bus, and RD and WR signals are generated as required.
KS152JB Universal Communications Controller Technical Specifications DMA CHANNEL 1 DMA CHANNEL 0 DARHO DARLO DARH1 DESTINATION ADDRESS SARHO DESTINATION ADDRESS SARH1 SARLO SOURCE ADDRESS BCRHO SARL1 SOURCE ADDRESS BCRH1 BCRLO BCRL1 BYTE COUNT BYTE COUNT DCON1 DCONO DMAO CONTROL DARL1 PCON DMA1 CONTROL Two new bits in PCON control Hold/Hold Acknowledge logic DMA Registers Two bits in DCONn are used to specify the physical destination of the data transfer.
KS152JB Universal Communications Controller Technical Specifications DAS IDA Destination Auto-Increment 0 0 1 1 0 1 0 1 External RAM External RAM SFR Internal RAM no yes no yes SAS ISA Source Auto-Increment 0 0 1 1 0 1 0 1 External RAM External RAM SFR Internal RAM no yes no yes There are four modes in which the DMA channel can operate.
KS152JB Universal Communications Controller Technical Specifications during the DMA, so interrupt flags may get set, but since program execution is suspended, the interrupts will not be serviced while the DMA is in progress. 4.1.3 SERIAL PORT DEMAND MODE In this mode the DMA can be used to service the Local Serial Channel (LSC) or the Global Serial Channel (GSC).
KS152JB Universal Communications Controller Technical Specifications is still 1 and the DONE bit is still 0. An external interrupt is not generated in this case, since in level-activated mode, pulling the pin to a logical 1 clears the interrupt flag. If the interrupt pin is then pulled low again, DMA transfers will continue from where they were previously stopped.
KS152JB Universal Communications Controller Technical Specifications DMA Transfer from Internal Memory to External Memory 12 OSC. PERIODS ALE PSEN P0 INST P2 PCH PCL DMA DATA OUT DARHn INST PCH WR RESUME PROGRAM EXECUTION DMA CYCLE 12 OSC. PERIODS ALE PSEN PO INST P2 SARLn FLOAT PCH DATA INFLOAT INST PCL PCH SARHn RD RESUME PROGRAM EXECUTION DMA CYCLE DMA Transfer from External Memory to Internal Memory DMA Transfer from External Memory to External Memory 12 OSC.PERIODS 12 OSC.
KS152JB Universal Communications Controller Technical Specifications 4.3 Hold/Hold Acknowledge Two operating modes of Hold/Hold Acknowledge logic are available, and either or neither may be invoked by software. In one mode, the C152 generates a Hold Request signal and awaits a Hold Acknowledge response before commencing a DMA that involves external RAM. This is called the Requester Mode.
KS152JB Universal Communications Controller Technical Specifications The functions of the ARB and REQ bits in PCON, then, are ARB REQ 0 0 1 1 0 1 0 1 Hold/Hold Acknowledge Logic Disabled C152 generates HLD, detects HLDA C152 detects HLD, generates HLDA Invalid 4.3.3 USING THE HOLD/HLDA ACKNOWLEDGE The HOLD/HOLDA logic only affects DMA operation with external RAM and don’t affect other operations with external RAM, such as MOVX instruction.
KS152JB Universal Communications Controller Technical Specifications selects which CPU’s ALE signal will be directed to the address latch. The Arbiter’s ALE is selected if HLDA is high, and the Requester’s ALE is selected if HLDA is low. The ALE Switch logic can be implemented as shown in below. ALE (ARB) ALE (ARB) IF HLDA = 1 HLDA ALE (AEQ) IF HLDA = 0 ALE (REQ) 4.3.4 INTERNAL LOGIC OF THE ARBITER The internal logic of the arbiter is shown in figure below.
KS152JB Universal Communications Controller Technical Specifications HLD Input CPU Osc. Periods Clock 1 Clock 2 HLDA Output 2 Osc. Periods 4 Osc. Periods When the arbiter wants to DMA the XRAM, it first activates DMXRQ. This signal prevents Q2 from being set if it is not already set.An output low from Q2 enables the arbiter to carry out its DMA to XRAM, and maintains an output high at HLDA.
KS152JB Universal Communications Controller Technical Specifications If the DMA is in alternate cycles mode, then each time DMA cycle is completed DMXRQ goes to 0, thus de-activating HLD. Once HLD has been de-activate, it can’t be re-asserted till after HLDA has been to go high (through flip-flop Q1A).
KS152JB Universal Communications Controller Technical Specifications Cycle is executed, on-chip arbitration logic determines which type of cycle is to be executed next. Note that when an instruction is executed, if the instruction wrote to a DMA register (excluding PCON), then another instruction is executed without further arbitration.
KS152JB Universal Communications Controller Technical Specifications mode_logic (n) if (DCONn indicates burst_mode) return 1: else if (DCONn indicates external_demand_mode) { if (demand_flag = 1) return 1: else return 0; } else if (DCONn indicates SP_demand_mode) { if {SARn = SBUF .AND. RI = 1) return 1; else if (DARn = SBUF .AND. TI = 1) return 1; else if (SARn = RFIFO .AND. RFNE = 1) return 1; else if (DARn = TFIFO .AND. TFNE = 1 .AND.
KS152JB Universal Communications Controller Technical Specifications If the test for SARn = SBUF is true, and if the flag RI is set, mode_logic (n) returns as 1 and the remainder of the function is not executed. Otherwise, execution proceeds to then exit if-condition, testing DARn against SBUF and T1 against 1. The same considerations regarding SAS and ISA in the SARn test are now applied to DAS and IDA in the DARn test. If SFR space isn’t selected, no Serial Port buffer is being addressed.
KS152JB Universal Communications Controller Technical Specifications decides it wants to do Burst mode DMA. The sequence of events might be: Instruction cycle (sets GO bit in DCON1) Instruction cycle (during which TFNF gets set) DMA0 cycle DMA1 cycle DMA1 cycle DMA1 cycle ...... DMA1 cycle (completes channel 1 burst) Instruction cycle DMA0 cycle Instruction cycle ........... This sequence begins with two Instruction cycles.
KS152JB Universal Communications Controller Technical Specifications hold_holda ( ): if (ARB = 0 .AND. REQ = 0) return 1; if SARn = XRAM .OR. DARn =XRAM) { if (ARB =1 .AND. HLDA = 1) return 1; if (REQ = 1 .AND. HLDA = 0) return 1; else return 0 ; } return 1; end hold_holda( ) ; 4.5 Summary of DMA Control Bits DCONs DAS IDA SAS ISA DM TM DONE GO DAS specifies the Destination Address Space. If DAS = 0, the destination is in External Data Memory.
KS152JB Universal Communications Controller Technical Specifications PCON SMOD ARB REQ GAREN XRCLK GFIEN PDN IDL ARB enables the DMA logic to detect HLD and generate HLDA. After it has activated HLDA, the C152 will not begin a new DMA to or from External Data Memory as long as HLD is seen to be active. This logic is disabled when ARB = 0, and enabled when ARB = 1. REQ enables the DMA logic to generate HLD and detect HLDA before performing a DMA to or from External Data Memory.
KS152JB Universal Communications Controller Technical Specifications As shown in Figure above, the Receive Valid interrupt can be signalled either by the RFNE flag (Receive FIFO Not Empty), or by the RDN flag (Receive Done). Which one of these flags causes the interrupt depends on the setting of the DMA bit in the SFR named TSTAT. DMA = 0 means the DMA hardware is not configured to service the GSC, so the CPU will service it in software in response to the Receive FIFO not being empty.
KS152JB Universal Communications Controller Technical Specifications Table 14: Interrupt Location Name DMA1 0053H DMA Channel 1 Done TF1 001BH Timer 1 Overflow GSCTE 004BH GSC Transmit Error TI+RI 0023H UART Transmit/Receive Note that the locations of the basic 8051 interrupts are the same as in the rest of the MCS-51 Family. And relative to each other they retain the same positions in the polling sequence.
KS152JB Universal Communications Controller Technical Specifications = 0 Disable EGSRE = 1 Enable GSC Receive Error Interrupt = 0 Disable EGSRV = 1 Enable GSC Receive Valid Interrupt = 0 Disable The two Interrupt Priority registers in the 8XC152 are as follows: 7 6 IP: 5 4 PS 3 PT1 2 PX1 1 PT0 0 PX0 Address of IP in SFR space = 0B8H (bit-addressable) 7 IPN1: 6 5 4 3 2 1 0 PGSTE PDMA1 PGSTV PDMA0 PGSRE PGSRV Address of IPN1 in SFR space = 0F8H (bit -addressable) The bits in IP are unchanged from
KS152JB Universal Communications Controller Technical Specifications It is recommended that user software should never write 1s to unimplemented bits in MCS-51 devices. Further versions of the device may have new bits installed in these locations. If so, their reset value will be 0. Old software that writes 1s to newly implemented bits may unexpectedly invoke new features. The MCS-51 interrupt structure provides hardware support for only two priority levels, High and Low.
KS152JB Universal Communications Controller Technical Specifications The UR bit can be set only if the DMA bit in the TSTAT is set. The DMA bit being set informs the GSC hardware that TFIFO is being serviced by DMA. In that case if the GSC goes to fetch another byte from TFIFO and finds it empty, and the byte count register of the DMA channel servicing TFIFO is not zero, it sets the UR bit. If the DMA hardware is not being used to service TFIFO, the UR bit cannot get set.
KS152JB Universal Communications Controller Technical Specifications RDN from being set. CRCE AE RCABT OVR GSCRE Clear GREN GREN Set RDN EOF RECEIVED Receive Error Flag (Logic for Clearing GREN, Setting RDN) A CRC Error means the CRC generator did not come to its correct value after calculating the CRC of the message plus received CRC. An alignment error means the number of bits received between the BOF and EOF was not a multiple of 8.
KS152JB Universal Communications Controller Technical Specifications AL - Address Length, see GMOD. AMSK0,1 (0D5H, 0E5H) - Address Match Mask 0,1 - Identifies which bits in ADR0,1 are “don’t care” bits. Setting a bit to 1 in AMSK0,1 identifies the corresponding bit in ADDR0,1 as not to be examined when comparing address. BAUD - (94H) Contains the programmable value for the baud rate generator for the GSC. The baud rate will equal (fosc) / ((BAUD+1) x 8).
KS152JB Universal Communications Controller Technical Specifications DCON0/1 (092H,093H) 7 DAS 6 IDA 5 SAS 4 ISA 3 DM 2 TM 1 DONE 0 GO The DCON register control the operation of the DMA channels by determining the source of data to be transferred, the destination of the data to be transfer, and the various modes of operation. DCON.0 (GO) - Enables DMA Transfer - When set it enables a DMA channel. If block mode is set then DMA transfer starts as soon as possible under CPU control.
KS152JB Universal Communications Controller Technical Specifications P1.2 is programmed to a 1. DM - DMA Mode, see DCON0 DMA - Direct Memory Access mode, see TSTAT. DONE - DMA done bit, see DCON0. DPH - Data Pointer High, an SFR that contains the high order byte of a general purpose pointer called the data pointer(DPTR). DPL - Data Pointer Low, an SFR that contains the low order byte of the data pointer. EDMA0 - Enable DMA Channel 0 interrupt, see IEN1. EDMA1 - Enable DMA Channel 1 interrupt, see IEN1.
KS152JB Universal Communications Controller Technical Specifications GMOD.0 (PR) - Protocol - If set SDLC protocols with NRZI encoding, zero bit insertion, and SDLC flags are used. If cleared, CSMA/CD link access with Manchester encoding is used. GMOD.1,2 (PL0,1) - Preamble length PL1 PL0 LENGTH (BITS) 0 0 0 0 1 8 1 0 32 1 1 64 The length includes the two bit Begin of Frame (BOF) flag in CSMA/CD but does not include SDLC flag. In SDLC mode, the BOF is an SDLC flag, otherwise it is two consecutive ones.
KS152JB Universal Communications Controller Technical Specifications added to the 8051BH core to accomplish high-speed transfers of packetized serial data. GTxD - GSC Transmit Data output, an alternate function of one of the port 1 pins (P1.1). This pin is used as the transmit output for the GSC. P1.1 must be programmed to a 1 for this function to operate. HBAEN - Hard Ware Based Acknowledge Enable, see RSTAT. HLDA - Hold Acknowledge, an alternate function of one of the port 1 pins (P1.6).
KS152JB Universal Communications Controller Technical Specifications IEN1 (0C8H) 7 6 5 4 3 2 1 0 EGSTE EDMA1 EGSTV EDMA0 EGSRE EGSRV Interrupt enable register for DMA and GSC interrupts. A 1 in any bit position enables that interrupt. IEN1.0 (EGSRV) - Enables the GSC valid receive interrupt. IEN1.1 (EGSRE) - Enables the GSC receive error interrupt. IEN1.2 (EDMA0) - Enables the DMA done interrupt for channel 0. IEN1.3 (EGSTV) - Enables the GSC valid transmit interrupt. IEN1.
KS152JB Universal Communications Controller Technical Specifications IPN1 (0F8H) 7 6 5 4 3 2 1 0 PGSTE PDMA1 PGSTV PDMA0 PGSRE PGSRV Allows the user software two levels of prioritization to be assigned to each of the interrupts in IEN1. A 1 assigns the corresponding interrupt in IEN1 a higher interrupt than an interrupt with a corresponding 0. IPN1.0 (PGSRV) - Assigns the priority of GSC receive valid interrupt. IPN1.1 (PGSRE) - Assigns the priority of GSC error receive interrupt. IPN1.
KS152JB Universal Communications Controller Technical Specifications MYSLOT.7 (DCJ) - Determines the type of Jam used during CSMA/CD operation when a collision occurs. If set to a 1 then a low D.C level is used as the jam signal. If cleared, then CRC is used as the jam signal. The jam is applied for a length of time equal to the CRC length. NOACK - No Acknowledgment error bit, see TSTAT.
KS152JB Universal Communications Controller Technical Specifications PGSRV - Priority bit for GSC Receive Valid interrupt see IPN1. PGSTE - Priority bit for GSC Transmit Valid interrupt, see IPN1. PL0 - One of the two bits that determines the Preamble Length, see GMOD. PL1 - One of the two bits that determines the Preamble Length, see GMOD. PRBS - (0E4H) - Pseudo-Random Binary Sequence generates the pseudo-random number to be used in CSMA/CD backoff algorithms.
KS152JB Universal Communications Controller Technical Specifications GREN has no effect on whether the receiver detects a collision in CSMA/CD mode as the receiver input circuitry always monitors the receive pin. RSTAT.2 (RFNE) - Receive FIFO Not Empty - If set, indicates that the receive FIFO contains data. The receive FIFO is a three byte buffer into which the receive data is loaded. A CPU read of the FIFO retrieves the oldest data and automatically updates the FIFO pointers.
KS152JB Universal Communications Controller Technical Specifications SCON (098H) 7 6 SM0 SM1 5 4 SM2 REN 3 TB8 2 1 RB8 TI 0 RI SCON.0 (RI) - Receive Interrupt Flag. SCON.1 - Transmit Interrupt Flag. SCON.2 (RB8) - Receive Bit 8, contains the ninth bit that was received in Modes 2 and 3 and stop bit in Mode 1 if SM20. Not used in Mode 0. SCON.3 (TB8) - Transmit Bit 8, the ninth bit to be transmitted in Modes 2 and 3. SCON.4 (REN) - Receive Enable, enables reception for the LSC. SCON.
KS152JB Universal Communications Controller Technical Specifications TCON.3 (IE1) - External Interrupt 1 edge flag. TCON.4 (TR0) - Timer 0 run control bit. TCON.5 (TF0) - Timer 0 overflow flag. TCON.6 (TR1) - Transmit Done flag, see TSTAT. TCON.7 (TF1) - Timer 1 overflow flag. TDN - Transmit Done Flag, see TSTAT TEN - Transmit Enable bit, see TSTAT. TFNF - Transmit FIFO Not Full Flag, see TSTAT. TFIFO - (85H) TFIFO is a 3 byte FIFO that contains the transmission data for the GSC.
KS152JB Universal Communications Controller Technical Specifications TMOD7 (GATE) - Gating Mode bit for Timer 1. TSTAT (0D8H) - Transmit Status Register 7 LNI 6 5 NOACK UR 4 3 2 1 TCDT TDN TFNF TEN 0 DMA TSTAT.0 (DMA) - DMA Select - If set, indicates that DMA channels are used to service the GSC FIFO’s and GSC interrupts occur on TDN and RDN, and also enables UR to become set. If cleared, indicates that the GSC is operating in it normal mode and interrupt occur on TFNE and RFNE.
KS152JB Universal Communications Controller Technical Specifications UR - Underrun Flag, see TSTAT. XRCLK - External GSC Receive Clock Enable bit, see PCON. XTCLK - External GSC Transmit Clock Enable bit, see GMOD. ............................... PORT 0 Bit: 7 6 5 4 3 2 1 0 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 Mnemonic: P0 Address: 80h Port 0 is used as the multiplexed address/data bus for external access.
KS152JB Universal Communications Controller Technical Specifications DATA POINTER HIGH Bit: 7 6 5 4 3 2 1 0 DPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0 Mnemonic: DPH Address: 83h This is the high byte of the 16-bit data pointer. The DPH is reset to 00h by a reset. There is unrestricted read/write access to this SFR.
KS152JB Universal Communications Controller Technical Specifications TIMER MODE CONTROL Bit: 7 6 5 4 3 2 1 0 GATE C/T M1 M0 GATE C/T M1 M0 TIMER 1 TIMER 0 Mnemonic: TMOD Address: 89h GATE Gating control: When this bit is set, Timer/counter x is enabled only while INTx pin is high and TRx control bit is set. When cleared, Timerx is enabled whenever TRx control bit is set. Timer or Counter Select: When cleared, the timer is incremented by internal clocks.
KS152JB Universal Communications Controller Technical Specifications TL1.7-0 Timer 1 LSB The TL1 sfr is set to 00h on any reset. There is unrestricted read/write access to this SFR. TIMER 0 MSB 7 6 5 4 3 2 1 0 TH0.7 TH0.6 TH0.5 TH0.4 TH0.3 TH0.2 TH0.1 TH0.0 Bit: Mnemonic: TH0 Address: 8Ch TH0.7-0 Timer 0 MSB The TH0 sfr is set to 00h on any reset. There is unrestricted read/write access to this SFR. TIMER 1 MSB Bit: 7 6 5 4 3 2 1 0 TH1.7 TH1.6 TH1.5 TH1.4 TH1.3 TH1.2 TH1.
KS152JB Universal Communications Controller Technical Specifications SERIAL PORT CONTROL Bit: 7 6 5 4 3 2 1 0 SM0 SM1 SM2 REN TB8 RB8 TI RI Mnemonic: SCON Address: 98h SM0 SM1 Serial port, Mode 0 bit: The operation of SM0 is described below. .
KS152JB Universal Communications Controller Technical Specifications The SBUF sfr is set to 00h by a reset. There is unrestricted read/write access to this SFR. PORT 2 Bit: 7 6 5 4 3 2 1 0 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 Mnemonic: P2 Address: A0h P2.7-0 Non-multiplexed address bus A15-A8: The port latch cannot be used for general I/O purposes but exists to support the MOVX instructions. Port 2 data will only be brought out on the P2.7-0 pins during indirect MOVX instructions.
KS152JB Universal Communications Controller Technical Specifications CY Carry flag: Set for an arithmetic operation which results in a carry being generated from the ALU. It is also used as the accumulator for the bit operations. AC Auxiliary carry: Set when the previous operation resulted in a carry (during addition0 or a borrow (during subtraction) from the high order nibble. F0 User flag 0: General purpose flag that can be set or cleared by the user by software. RS.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 119 of 120 Ver. 0.
KS152JB Universal Communications Controller Technical Specifications Kawasaki LSI USA, Inc. Page 120 of 120 Ver. 0.
