User manual

Section 13: Instrument Control Library (ICL) Series 3700 System Switch/Multimeter Reference Manual
13-276 3700S-901-01 Rev. C / July 2008
status.questionable.*
.condition
.enable
.event
.ntr
.ptr
Details
quesreg can be set to the decimal weight of the bit to be set:
To set bit B1 (S1INL), set quesreg to 1 (2
1
).
To set bit B2 (S2INL), set quesreg to 4 (2
2
).
To set bit B3 (S3INL), set quesreg to 8 (2
3
).
To set bit B4 (S4INL), set quesreg to 16 (2
4
).
To set bit B5 (S5INL), set quesreg to 32 (2
5
).
To set bit B6 (S6INL), set quesreg to 64 (2
6
).
To set bit B7 (DMMCON), set quesreg to 128 (2
7
).
To set bit B8 (CAL), set quesreg to 256 (2
8
).
To set bit B9 (S1THR), set quesreg to 512 (2
9
).
To set bit B10 (S2THR), set quesreg to 1024 (2
10
).
To set bit B11 (S3THR), set quesreg to 2048 (2
11
).
To set bit B12 (S4THR), set quesreg to 4096 (2
12
).
To set bit B13 (S5THR), set quesreg to 8192 (2
13
).
To set bit B14 (S6THR), set quesreg to 16384 (2
14
).
To set more than one bit of the register, set quesreg to the sum of their decimal
weights. For example, to set bits B8 and B12, set quesreg to 4352 (256 + 4096).
Example
To set the CAL bit of the questionable enable register:
status.questionable.enable = status.questionable.CAL