Datasheet

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Benets

• −30°Cto+85°Coperatingtemperaturerange

• Lead (Pb)-free, RoHS and REACH compliant

• EIA 0402, 0603, 0805, 1206, and 1210 case sizes

• DCvoltageratingsof6.3V,10V,16V,25V,and50V

• Capacitanceofferingsrangingfrom0.022μFto22μF

• Availablecapacitancetoleranceof±20%and+80%/−20%

• Non-polardevice,minimizinginstallationconcerns

• 100%puremattetin-platedterminationnishthatallows

for excellent solderability

Applications

Typicalapplicationsincludelimitedtemperature,decoupling

and bypass.

Overview

KEMET’sY5Vdielectricfeaturesan85°Cmaximum

operatingtemperatureandisconsidered“general-purpose.”

TheElectronicsIndustriesAlliance(EIA)characterizes

Y5VdielectricasaClassIIImaterial.Componentsofthis

classicationarexed,ceramicdielectriccapacitors,

suitedforbypassanddecouplingorotherapplications

inwhichdielectriclosses,highinsulationresistanceand

capacitance stability are not of major importance. Y5V

exhibitsapredictablechangeincapacitancewithrespectto

timeandvoltage,anddisplayswidevariationsincapacitance

withreferencetoambienttemperature.Capacitancechange

islimitedto+22%,−82%from−30°Cto+85°C.

SurfaceMountMultilayerCeramicChipCapacitors(SMDMLCCs)

Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)

Ordering Information

C 1210 C 226 Z 4 V A C TU

Ceramic

Case Size

(L" x W")

Specication/

Series

Capacitance

Code(pF)

Capacitance

Tolerance

Rated

Voltage

(VDC)

Dielectric

FailureRate/

Design

TerminationFinish

Packaging/

Grade (C-Spec)

0402

0603

0805

1206

1210

C = Standard Twosignicant

digits+number

of zeros

M = ±20%

Z=+80%/−20%

9 = 6.3

8 = 10

4 = 16

3 = 25

5 = 50

V = Y5V A = N/A C = 100% Matte Sn See

"Packaging

C-Spec

Ordering

Options

Table" below

Additional termination nish options may be available. Contact KEMET for details.

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Summary of content (17 pages)

PAGE 1
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Overview KEMET’s Y5V dielectric features an 85°C maximum operating temperature and is considered “general-purpose.” The Electronics Industries Alliance (EIA) characterizes Y5V dielectric as a Class III material.
PAGE 2
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) Y5V Dielectric, 6.
PAGE 3
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Qualification/Certification Commercial Grade products are subject to internal qualification. Details regarding test methods and conditions are referenced in Table 4, Performance & Reliability. Environmental Compliance Lead (Pb)-free, RoHS, and REACH compliant without exemptions.
PAGE 4
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Table 1 – Capacitance Range/Selection Waterfall (0402 – 1210 Case Sizes) 5 9 8 4 3 5 50 3 25 4 16 8 10 9 6.
PAGE 5
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Table 2A – Chip Thickness/Tape & Reel Packaging Quantities Paper Quantity1 Plastic Quantity Thickness Code Case Size Thickness ± Range (mm) 7" Reel 13" Reel 7" Reel 13" Reel BB CF CG DN DO DP DL DF DG EB EC ED EP EH EJ FD FE FF FG FH FJ FT FS 0402 0603 0603 0805 0805 0805 0805 0805 0805 1206 1206 1206 1206 1206 1206 1210 1210 1210 1210 1210 1210 1210 1210 0.50 ± 0.05 0.80 ± 0.07* 0.
PAGE 6
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) Y5V Dielectric, 6.
PAGE 7
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Table 3 – Chip Capacitor Land Pattern Design Recommendations per IPC-7351 EIA Size Code Metric Size Code 0402 Density Level A: Maximum (Most) Land Protrusion (mm) Density Level B: Median (Nominal) Land Protrusion (mm) Density Level C: Minimum (Least) Land Protrusion (mm) C Y X V1 V2 C Y X V1 V2 C Y X V1 V2 1005 0.50 0.72 0.72 2.20 1.20 0.45 0.62 0.62 1.90 1.00 0.
PAGE 8
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Soldering Process Recommended Soldering Technique: • Solder wave or solder reflow for EIA case sizes 0603, 0805 and 1206 • All other EIA case sizes are limited to solder reflow only Recommended Reflow Soldering Profile: KEMET’s families of surface mount multilayer ceramic capacitors (SMD MLCCs) are compatible with wave (single or dual), convection, IR or vapor phase reflow techniques.
PAGE 9
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Table 4 – Performance & Reliability: Test Methods and Conditions Stress Reference Test or Inspection Method Terminal Strength JIS–C–6429 Appendix 1, Note: Force of 1.8 kg for 60 seconds. Board Flex JIS–C–6429 Appendix 2, Note: Standard termination system – 2.0 mm (minimum) for all except 3 mm for C0G. Flexible termination system – 3.0 mm (minimum). Magnification 50 X.
PAGE 10
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) Y5V Dielectric, 6.
PAGE 11
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Tape & Reel Packaging Information KEMET offers multilayer ceramic chip capacitors packaged in 8, 12 and 16 mm tape on 7" and 13" reels in accordance with EIA Standard 481. This packaging system is compatible with all tape-fed automatic pick and place systems. See Table 2 for details on reeling quantities for commercial chips.
PAGE 12
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Figure 1 – Embossed (Plastic) Carrier Tape Dimensions P2 T T2 ØD0 (10 pitches cumulative tolerance on tape ±0.2 mm) P0 A0 E1 F K0 B1 E2 B0 S1 W P1 T1 Center Lines of Cavity ØD1 Cover Tape B1 is for tape feeder reference only, including draft concentric about B0.
PAGE 13
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Figure 2 – Punched (Paper) Carrier Tape Dimensions T Po ØDo (10 pitches cumulative tolerance on tape ±0.
PAGE 14
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Packaging Information Performance Notes 1. Cover Tape Break Force: 1.0 kg minimum. 2. Cover Tape Peel Strength: The total peel strength of the cover tape from the carrier tape shall be: Tape Width Peel Strength 8 mm 0.1 to 1.0 newton (10 to 100 gf) 12 and 16 mm 0.1 to 1.3 newton (10 to 130 gf) The direction of the pull shall be opposite the direction of the carrier tape travel.
PAGE 15
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Figure 6 – Reel Dimensions Full Radius, See Note W3 (Includes flange distortion at outer edge) Access Hole at Slot Location (Ø 40 mm minimum) W2 D A (See Note) N C (Arbor hole diameter) B (see Note) (Measured at hub) W1 (Measured at hub) If present, tape slot in core for tape start: 2.5 mm minimum width x 10.
PAGE 16
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) Y5V Dielectric, 6.
PAGE 17
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) KEMET Electronics Corporation Sales Oﬃces For a complete list of our global sales oﬃces, please visit www.kemet.com/sales. Disclaimer All product specifications, statements, information and data (collectively, the “Information”) in this datasheet are subject to change.