Manual
122
Lake Controller Operation Manual Rev 1.5.4
Modules Menu Reference
Other Lake devices on the network that have Dante enabled will be Dante slaves, and the clock will report
that it is overridden by Dante, as shown in Figure 8-6. Any other 96 kHz signal, or 44.1 kHz based signal
should be locked using the SRC Clock (applicable for LM Series only).
Figure 8-6: Primary Clock as Dante Slave
For PLM+ and D Series with Dante enabled, the Primary Clock will always lock to Dante; the device can still
be a Dante master, but the internal clock will be used to lock the Primary Clock. Any external digital input
must use the Sample Rate Convertor Clock.
8.2.1.4 Host Clock (MY8-LAKE only)
The highest priority auto-clock selection for the MY8-LAKE device is the Host Clock as shown in section
8.2.1.1. For the MY8-LAKE device, the Primary Clock can only lock to a source operating in multiples of
48 kHz, and the Sample Rate Convertor Clock can only lock to a source operating in multiples of 44.1 kHz.
Ensure that AES & Host clocks operating at the same base-rate (e.g. multiples of 48 kHz) are in-phase to
avoid any clock slipping errors.
8.2.2 Input Conguration
Each input may be congured to use any available input source. Sources include AES/EBU digital inputs,
Dante inputs, analog inputs, and Host digital inputs (MY8-LAKE only).
To access the input conguration, tap the zoom button, or any area of the INPUT CONFIGURATION sum-
mary text on the I/O CONFIG screen shown in Figure 8-7.