Operation Manual

10. Application Guide
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It is recommended that all cables be tested for error-free performance at lengths 20% to 25% greater than lengths
10.5.4. External Signal Distribution Hardware
10.5.4.1. Distribution Amplifiers
format is one input and six outputs. Digital distribution ampli
as well making up for line losses.
times the signal to prevent signal degradation from clocking errors known as jitter.
small additional amounts of latency, so should not be used unless necessary.
10.5.4.2. Passive splitters
One single AES3 input may be split into more signals using a simple passive splitter. Splitters provide a convenient
and low cost solution when only a few additional signals are required, and in situations where cable lengths are
short. Attenuation is minimal, but there is no refreshing of the signal.
10.5.5. Additional Reference Material
Complete technical information on the AES/EBU (AES3) standard can be downloaded from the AES web site at
http://www.aes.org/publications/standards/.
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10.6. Digital Clock Configuration
10.6.1. Digital Clock Overview
clocking system. The digital clock can generate various independent internal sample rates, or can sync to an
incoming AES3 signal. Figure 10.7 shows the various sample rates and options available.
INPUTS
DANTE
C
AES1
48 kHz
AES2
INTERNAL
PRIMARY
CLOCK
48 kHz
96 kHz
192 kHz
C
AES1
48 kHz
AES2
INTERNAL
48 kHz
96 kHz
192 kHz
44.1 kHz
88.2 kHz
176.4 kHz
44.1 kHz
INTERNAL
Pwr 1
C
Pwr 2
C
Pwr 3
C
Pwr 4
C
Dante
C
Channel 1-8
48 / 96 kHz
OUTPUTS
SAMPLE RATE
CONVERTER
CLOCK
C
AUTO /
MANUAL 48
C
AUTO /
MANUAL 44
Table 10.7: Digital Clocking System
In Figure 10.7, each circled C represents a choice point. A choice point is a user-interface control that can be
information.
NOTE: Figure 10.7 indicates internally generated clocks with base-rate multiples of 44.1 kHz or 48 kHz.
This should not be confused with the internal DSP sample rate of 96 kHz.
The PLM+ digital clocking system can either generate its own internal clock, or synchronize to an incoming
external clock source via the AES3 digital input.
10.6.2. Clock Source Priorities
compatible clock signal is preset.
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