Data Sheet

LWB5+
Datasheet
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10.1.4 SDR50Mode(50MHz)(1.8V)
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Figure 6: SDIO CMD timing diagram--- SDR50 modes (50 MHz) (1.8V)
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Figure 7: SDIO DAT[3:0] timing Diagram--- SDR50 modes (50 MHz) (1.8V)
Note: In SDR50 mode, DAT[3:0] lines are samples on both edges pf the clock (not applicable for CMD line)
Table 23: SDIO timing requirements – SDR50 modes (50 MHz)
Symbol Parameter Condition Min. Typ. Max. Unit
Clock
T CLK
Clock time
50MHz (max) between rising edge
SDR50 20 -- -- ns
T CR , T CF
Rise time, fall time
T
CR , T CF <4.00ns (max) at 50MHz.
C
CARD =10pF
SDR50 -- -- 0.2*T
CLK ns
Clock Duty -- SDR50 45 -- 55 %
CMD Input (referenced to clock rising edge)
T IS
Input setup time
C CARD ≦10pF (1 card)
SDR50 6 -- -- ns
T IH
Input hold time
C CARD ≦10pF (1 card)
SDR50 0.8 -- -- ns