A Version 1.
Version Date 1.0 18 Feb 2022 https://www.lairdconnect.
1 Introduction .......................................................................................................................................................................... 5 1.1 Key Features .............................................................................................................................................................. 5 1.2 Hardware Features.........................................................................................................................
8 9 10 7.1 Layout and Placement.............................................................................................................................................. 32 7.2 Best Design Practices .............................................................................................................................................. 35 7.3 Internal Antenna Radio Performance vs. Carrier Board Size ................................................................................... 37 7.
The Lyra S is a module designed and built to meet the performance, security, and reliability requirements of battery-powered IoT products running on Bluetooth networks. Based on the EFR32BG22 SoC, the Lyra S enables Bluetooth® Low Energy connectivity while delivering best-in-class RF range and performance, future-proof capability for feature and OTA firmware updates, enhanced security features, and low energy consumption.
▪ ▪ ▪ ▪ ▪ Supported Protocols – Bluetooth Low Energy (Bluetooth 5.3) Direction finding 1M, 2M, and LE Coded PHYs Bluetooth Mesh Low Power Node Wireless System-on-Chip – 2.4 GHz radio – TX power up to 6 dBm – High-performance 32-bit ARM Cortex-M33® with DSP instruction and floating-point unit for efficient signal processing – Up to 512 kB flash program memory – 32 kB RAM data memory – Embedded Trace Macrocell (ETM) for advanced debugging High Receiver Performance – -106.4 dBm sensitivity (0.
Table 1: Ordering Information Part Description 453-00091R Lyra Series - Bluetooth v5.3 SIP Module with antenna options (Silicon Labs EFR32BG22) - Tape / Reel 453-000091C Lyra Series - Bluetooth v5.3 SIP Module with antenna options (Silicon Labs EFR32BG22) – Cut / Tape 453-00091-K1 Lyra Series - Development Kit - Bluetooth v5.3 SIP Module with antenna options https://www.lairdconnect.
The Lyra S module combines an energy-friendly MCU with a highly integrated radio transceiver in a SiP module with a robust, integrated antenna. This section gives a short introduction to the features of the module. The block diagram for the Lyra S module is shown in the figure below. The wireless module includes the EFR32BG22 wireless System on a Chip (SoC), required decoupling capacitors and inductors, 38.4 MHz crystal, RF matching circuit, and integrated antenna.
The EFR32BG22 SoC features a 32-bit ARM Cortex M33 core, a 2.4 GHz high-performance radio, 512 kB of flash memory, a rich set of MCU peripherals, and various clock management and serial interfacing options. Consult the EFR32xG22 Wireless Gecko Reference Manual and the EFR32BG22 Data Sheet for details. Lyra S module includes an integral antenna on board with the characteristics detailed in the tables below.
All electrical parameters in all tables are specified under the following conditions, unless stated otherwise: ▪ ▪ Typical values are based on TA=25 °C and VREGVDD supply at 3.0 V, by production test and/or technology characterization. Minimum and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature, unless stated otherwise. Stresses beyond those listed below may cause permanent damage to the device.
This table specifies the general operating temperature range and supply voltage range for all supplies. The minimum and maximum values of all other tables are specified over this operating range, unless otherwise noted.
The maximum supported voltage on the VREGVDD supply pin is limited under certain conditions. Maximum input voltage is a function of temperature and the average load current over a 10-year lifetime. Figure 3 shows the safe operating region under specific conditions. Exceeding this safe operating range may impact the reliability and performance of the DC-DC converter. The average load current for an application can typically be determined by examining the current profile during the time the device is powered.
Unless otherwise indicated, typical conditions are: Module supply voltage = 3.0 V. Voltage scaling level = VSCALE1. T A = 25 °C. Minimum and maximum values in this table represent the worst conditions across process variation at T A = 25 °C.
Parameter Symbol Current consumption in EM4 mode IEM4 Additional current in EM2 or EM3 when any peripheral in PD0B is enabled1 IPD0B_VS Test Condition No BURTC, No LF Oscillator, DCDC bypassed Min Typ Max Unit — 0.17 — µA — 0.37 — µA Note: 1. Extra current consumed by power domain. Does not include current associated with the enabled peripherals. See for a list of the peripherals in each power domain. RF current consumption measured with MCU in EM1, HCLK = 38.
Unless otherwise indicated, typical conditions are: TA = 25 °C, VREGVDD = 3.0V. RF center frequency 2.45 GHz. Table 6: RF Transmitter General Characteristics for the 2.4 GHz Band Parameter Symbol Test Condition Min Typ Max Unit 2400 — 2483.5 MHz — 6.
Unless otherwise indicated, typical conditions are: TA = 25 °C, VREGVDD = 3.0V. RF center frequency 2.45 GHz. Table 8: RF Receiver Characteristics for Bluetooth Low Energy in the 2.
Unless otherwise indicated, typical conditions are: TA = 25 °C, VREGVDD = 3.0V. RF center frequency 2.45 GHz. Table 9: RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 2 Mbps Data Rate Parameter Symbol Test Condition Min Typ Max Unit signal1 — 10 — dBm Signal is reference signal, 37 byte payload2 — -95.9 — dBm Signal is reference signal, 255 byte payload1 — -94.3 — dBm With non-ideal signals3 1 — -94.0 — dBm — 8.
Unless otherwise indicated, typical conditions are: TA = 25 °C, VREGVDD = 3.0V. RF center frequency 2.45 GHz. Table 10: RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 500 kbps Data Rate Parameter Symbol Test Condition signal1 Min Typ Max Unit — 10 — dBm -102.3 — dBm — -100.9 — dBm — -99.8 — dBm — 2.
Unless otherwise indicated, typical conditions are: TA = 25 °C, VREGVDD = 3.0V. RF center frequency 2.45 GHz. Table 11: RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 125 kbps Data Rate Parameter Symbol Test Condition Min Typ Max Unit signal1 — 10 — dBm Signal is reference signal, 37 byte payload2 — -106.4 — dBm Signal is reference signal, 255 byte payload1 — -106.0 — dBm With non-ideal signals3 1 — -105.6 — dBm — 0.
Table 12: High-Frequency Crystal Parameter Symbol Test Condition Min Typ Max Unit Crystal frequency fHFXTAL — 38.
Table 14: Precision Low Frequency RC Oscillator (LFRCO) Parameter Symbol Nominal oscillation frequency FLFRCO Frequency accuracy FLFRCO_ACC Test Condition Typ Max Unit — 32.768 — kHz -3 — 3 % -500 — 500 ppm Normal mode — 204 — µs Precision mode1 — 11.7 — ms Normal mode — 175 — nA Precision mode1, T = stable at 25 °C 3 — 655 — nA Normal mode Precision mode1, across operating temperature range2 Startup time Current consumption tSTARTUP ILFRCO Min Note: 1.
Unless otherwise indicated, typical conditions are: IOVDD = 3.0 V. Table 15: GPIO Pins Parameter Symbol Leakage current ILEAK_IO Input low voltage1 VIL Input high voltage1 VIH Hysteresis of input voltage VHYS Output high voltage VOH Output low voltage VOL GPIO rise time TGPIO_RISE GPIO fall time Pull up/down resistance2 Maximum filtered glitch width TGPIO_FALL RPULL TGF Test Condition Min Typ Max Unit MODEx = DISABLED, IOVDD = 1.71 V — 1.9 — nA MODEx = DISABLED, IOVDD = 3.
The MCU peripherals set available in Lyra S modules includes: ▪ ▪ ▪ ▪ ▪ ▪ ADC: 12-bit at 1 Msps, 16-bit at 76.9 ksps 16-bit and 32-bit Timers/Counters 24-bit Low Energy Timer for waveform generation 32-bit Real Time Counter USART (UART/SPI/SmartCards/IrDA/I2S) EUART (UART/IrDA) ▪ ▪ ▪ I2C peripheral interfaces PDM interface 12 Channel Peripheral Reflex System For details on their electrical performance, consult the relevant portions of Section 4 in the SoC datasheet.
Typical Lyra S radiation patterns for the on-board chip antenna under optimal operating conditions are plotted in the figures that follow. Antenna gain and radiation patterns have a strong dependence on the size and shape of the application PCB the module is mounted on, as well as on the proximity of any mechanical design to the antenna. Phi 0o Phi 90o Theta 90o Figure 5: Lyra S Internal Antenna Typical 2D Antenna Radiation Patterns on 55 mm x 20 mm board https://www.lairdconnect.
The Lyra S can be controlled over the UART interface as a peripheral to an external host processor. Typical power supply, programming/debug interface, and host interface connections are shown in the figure below. Figure 6: UART NCP Configuration https://www.lairdconnect.
The Lyra S can be used in a stand-alone SoC configuration without an external host processor. Typical power supply and programming/debug interface connections are shown in the figure below. Figure 7: Stand-Alone SoC Configuration https://www.lairdconnect.
Figure 8: 44-Pin SiP Module Device Pinout The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see Alternate Function Table and Digital Peripheral Connectivity. Pin Name Pin(s) Description Pin Name Pin(s) Description NC 1 Do not connect ANT_IN 2 Antenna In RF_2G4 3 2.
Pin Name Pin(s) Description Pin Name Pin(s) Description VREG 21 DVDD, RFVDD, and PAVDD supply lines. It is not intended to power external circuitry. VREGVDD 22 to the SoC AVDD and VREGVDD supply lines. IOVDD 23 I/O power supply PD03 24 GPIO PD02 25 GPIO PD01 26 GPIO PD00 27 GPIO PC00 28 GPIO PC01 29 GPIO PC02 30 GPIO PC03 31 GPIO PC04 32 GPIO PC05 33 GPIO PC06 34 GPIO RESETn 35 Reset Pin. The RESETn pin is internally pulled up to VREG (DVDD).
A wide selection of alternate functionality is available for multiplexing to various pins. The following table shows what functions are available on each device pin. GPIO Alternate Functions PB03 GPIO.EM4WU4 PB01 GPIO.EM4WU3 PB00 IADC0.VREFN PA00 IADC0.VREFP PA01 GPIO.SWCLK PA02 GPIO.SWDIO PA03 GPIO.SWV GPIO.TDO GPIO.TRACEDATA0 PA04 GPIO.TDI GPIO.TRACECLK PA05 GPIO.EM4WU0 PD02 GPIO.EM4WU9 PD01 LFXO.LFXTAL_I LFXO.LF_EXTCLK PD00 PC00 LFXO.LFXTAL_O GPIO.EM4WU6 GPIO.
Many digital resources are routable and can be connected to numerous GPIO's. The table below indicates which peripherals are available on each GPIO port. Table 16: DBUS Routing Table Peripheral.Resource CMU.CLKIN0 CMU.CLKOUT0 CMU.CLKOUT1 CMU.CLKOUT2 EUART0.CTS EUART0.RTS EUART0.RX EUART0.TX FRC.DCLK FRC.DFRAME FRC.DOUT I2C0.SCL I2C0.SDA I2C1.SCL I2C1.SDA LETIMER0.OUT0 LETIMER0.OUT1 MODEM.ANT0 MODEM.ANT1 MODEM.ANT_ROLL_OVER MODEM.ANT_RR0 MODEM.ANT_RR1 MODEM.ANT_RR2 MODEM.ANT_RR3 MODEM.ANT_RR4 MODEM.
Peripheral.Resource PRS.ASYNCH7 PRS.ASYNCH8 PRS.ASYNCH9 PRS.SYNCH0 PRS.SYNCH1 PRS.SYNCH2 PRS.SYNCH3 TIMER0.CC0 TIMER0.CC1 TIMER0.CC2 TIMER0.CDTI0 TIMER0.CDTI1 TIMER0.CDTI2 TIMER1.CC0 TIMER1.CC1 TIMER1.CC2 TIMER1.CDTI0 TIMER1.CDTI1 TIMER1.CDTI2 TIMER2.CC0 TIMER2.CC1 TIMER2.CC2 TIMER2.CDTI0 TIMER2.CDTI1 TIMER2.CDTI2 TIMER3.CC0 TIMER3.CC1 TIMER3.CC2 TIMER3.CDTI0 TIMER3.CDTI1 TIMER3.CDTI2 TIMER4.CC0 TIMER4.CC1 TIMER4.CC2 TIMER4.CDTI0 TIMER4.CDTI1 TIMER4.CDTI2 USART0.CLK USART0.CS USART0.CTS USART0.RTS USART0.
For optimal performance of the Lyra S the following guidelines are recommended: ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ Place the module 1.50 mm from the edge of the copper “keep-in” area at the middle of the long edge of the application PCB, as illustrated in Figure 9. Copy the exact antenna design from Figure 9 with the values for coordinates A to L given in Figure 10. Make a cutout in all lower layers aligned with the right edge and the bottom edge of the antenna as indicated by the yellow box in Figure 11.
Figure 10: Internal Antenna Layout With Coordinates Table 17: Antenna Polygon Coordinates, Referenced to Center of Lyra S Point Lyra S A (2.87, 2.13) B (2.54, 2.13) C (2.54, 3.69) D (3.36, 4.51) E (7.75, 4.51) F (7.75, 4.15) G (6.84, 4.15) H (6.21, 3.52) I (4.26, 3.52) J (3.97, 3.81) K (3.10, 3.81) L (2.87, 3.58) Wloop 4.88 Hloop 4.15 Note: 1. All coordinates and dimensions listed in mm. https://www.lairdconnect.
Figure 11: Antenna Clearance in Inner and Bottom Layers https://www.lairdconnect.
The design of a good RF system relies on thoughtful placement and routing of the RF signals. The following guidelines are recommended: ▪ ▪ ▪ ▪ ▪ ▪ Place the Lyra S and antenna close to the center of the longest edge of the application board. Do not place any circuitry between the board edge and the antenna. Make sure to tie all GND planes in the application board together with as many vias as can be fitted.
Figure 13: Non-Optimal Layout Examples https://www.lairdconnect.
For many applications, the carrier board size is determined by the overall form factor or size of the additional circuitry. The recommended carrier board width 55 mm for the Lyra S is thus not always possible in the end-application. If another form factor is required, the antenna performance of the integrated antenna will be compromised but it may still be sufficiently good for providing the required link quality and range of the end-application.
Lyra S module can be used with external antennas (certified by Laird Connectivity), and requires a 50 Ohm RF trace (GCPW, that Grounded Coplanar Waveguide) to be designed to run from Lyra S module RF_2G4 (pin3) to a RF antenna connector (IPEX MHF4) on host PCB. The 50 Ohms RF track design and length MUST be copied (as specified in this section). On the RF path, 0R series resistor connects Lyra S module RF_2G4 (pin3) to RF track. Lyra S module GND pin4 and GND pin5 used to support GCPW 50Ohm RF trace.
Layer1 (RF Track and RF GND) Layer2 (RF GND) Figure 16: 50-Ohm RF trace design (Layer1 and Layer2) on DVK-Lyra S development board 453-00091-K1 (or host PCB) for use with Lyra S (453-00091) module Checklist for PCB: ▪ MUST use a 50-Ohm RF trace (GCPW, that is Grounded Coplanar Waveguide) from RF_2G4 pad (pin3) of the Lyra S module (453-00091) to RF antenna connector (IPEX MHF4 Receptable (MPN: 20449-001E)) on host PCB.
Solder Mask Layer1 Copper 1oz+plating Core 0.6mm Layer2 Copper 1oz+plating Solder Mask Thickness Dielectric mil Constant Er 1.18 3.5 1.3 59.06 4.2 1.3 1.18 Stack up for 50Ohms GCPW RF track. 3.5 Figure 17: Lyra S development board PCB stack-up and 50-Ohms Grounded CPW RF trace design using GND on L1 and L2 Note 1: The plating (ENIG) above base 1ounce copper is not listed, but plating expected to be ENIG.
Please refer to the Lyra S Regulatory Information Guide for details on using Lyra S module with external antennas in each regulatory region. The Lyra S has been designed to operate with the below external antennas (with a maximum gain of 2.0 dBi). The required antenna impedance is 50 ohms. See Table 18. External antennas improve radiation efficiency.
The package dimensions are shown in Figure 18. Figure 18: Mechanical Dimensions – Full https://www.lairdconnect.
The recommended PCB Land Pattern is shown in Figure 19. Figure 19: Module Land Pattern Notes: 1. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05mm is assumed. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 4. The stencil thickness should be 0.100 mm (4 mils). 5.
Figure 20: Lyra S Top Marking Table 19: Top Marking Definition Part Number 453-00091 Line 1 Marking 453-00091 Line 2 Marking Lyra-S Line 3 Marking See note below Note: YY = Year. WW = Work Week, TTTTTTT = Trace Code https://www.lairdconnect.
▪ ▪ ▪ ▪ Optimal solder reflow profile depends on solder paste properties and should be optimized as part of an overall process development. It is important to provide a solder reflow profile that matches the solder paste supplier's recommendations. Temperature ranges beyond that of the solder paste supplier's recommendation could result in poor solderability. All solder paste suppliers recommend an ideal reflow profile to give the best solderability. Figure 21: Recommended Reflow Profile https://www.
In general, cleaning the populated modules is strongly discouraged. Residuals under the module cannot be easily removed with any cleaning process. ▪ ▪ ▪ Cleaning with water can lead to capillary effects where water is absorbed into the gap between the host board and the module. The combination of soldering flux residuals and encapsulated water could lead to short circuits between neighboring pads. Water could also damage any stickers or labels.
Lyra S modules are delivered to the customer in Cut Tape (600 pcs) or reel (2500 pcs / reel) packaging with the dimensions below. All dimensions are given in mm unless otherwise indicated. Figure 22: Carrier Tape Dimensions Figure 23: Reel Dimensions https://www.lairdconnect.
Note: For complete regulatory information, refer to the Lyra S Regulatory Information document which is also available from the Lyra Series product page. The Lyra S holds current certifications in the following countries: Country/Region Regulatory ID USA (FCC) SQG-LyraS Canada (ISED) 3147A-LyraS UK (UKCA) N/A EU N/A Japan (MIC) 209-J00457 Korea (KC) R-C-L7C-LyraS https://www.lairdconnect.
The Lyra S Series module is listed on the Bluetooth SIG website as a qualified End Product, using the combination of a RFPHY, LL and Host Stack Components. Design Name Owner Declaration ID Lyra S Laird Connectivity D057227 Design Name BGM220S RF-PHY Wireless Gecko Link Layer Wireless Gecko Host Reference QDID 178495 178212 175341 Link to listing on the SIG website https://launchstudio.bluetooth.com/ListingDetails/147725 Owner Reference QDID Silicon Laboratories 178495 https://launchstudio.
6. Declaration ID: ▪ Select a Declaration ID from the list. Important! To complete this step, you must have already paid your Bluetooth SIG Declaration ID fee. If you have not, refer to the Bluetooth SIG Qualification Overview section for instructions. You also have the option of clicking Pay Declaration Fee accessible from this step of the Bluetooth SIG Qualification process. 7. Review and Submit – With this, some automatic checks occur to ensure all sections are complete.
Please contact your local sales representative or our support team for further assistance: Laird Connectivity Support Centre: https://www.lairdconnect.com/resources/support Email: wireless.support@lairdconnectivity.com Phone: Americas: +1-800-492-2320 Europe: +44-1628-858-940 Hong Kong: +852-2762-4823 Web: https://www.lairdconnect.com/products Note: Information contained in this document is subject to change. © Copyright 2022 Laird Connectivity. All Rights Reserved. Patent pending.