Data Sheet

RM1xx LoRa/BLE Modules
Datasheet
https://connectivity.lairdtech.com/wireless-
modules/lorawan-solutions
20
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4.2 Clocks and Timers
4.2.1 Clocks
The integrated high accuracy (+/-20 ppm) 32.768 kHz crystal oscillator provides protocol timing and helps with radio power
consumption in the system Standby Doze/Deep sleep modes by reducing the time that the RX window needs to be open.
Standard accuracy clocks tend to have lower accuracy +/-250 ppm.
The integrated high accuracy 16 MHz (+/-10 ppm) crystal oscillator helps with radio operation and also helps reduce power
consumption in the active modes.
4.2.2 Timers
In keeping with the event-driven paradigm of smartBASIC, the timer subsystem enables smartBASIC applications to be
written which allow future events to be generated based on timeouts.
 Regular Timer – There are eight built-in timers (regular timers) derived from a single RTC clock which are controlled
solely by smart
BASIC functions. The resolution of the regular timer is 976 microseconds.
 Tick Timer – A 31-bit free running counter that increments every one millisecond. The resolution of this counter is 488
microseconds. This counter can be accessed using the functions GetTickCount() and GetTickSince().
Refer to the smart
BASIC user guide for more information.
4.3 RF
 RM186 LoRa radio: 865 – 870 MHz (250 – 11000 bps over the air data rate)
 RM186 protocol can optionally employs 50 kbps FSK when enabled by the gateway
 RM191 Lora radio: 902 – 928 MHz (980 – 21900 bps over the air data rate)
 Bluetooth Low Energy radio: 2402–2480MHz (1 Mbps over the air data rate).
 BLE TX output power of +3 dBm programmable (via smartBASIC command) to -20 dBm in steps of four dB.
 BLE TX Whisper mode1 -30 dBm (via smartBASIC command).
 BLE TX Whisper mode2 -55 dBm (via smartBASIC command).
 BLE Receiver (with integrated channel filters) to achieve maximum sensitivity -91 dBm @ 1 Mbps BLE.
 BLE Antenna: Integrated monopole chip antenna on RM1xx
4.4 UART Interface
The Universal Asynchronous Receiver/Transmitter offers fast, full-duplex, asynchronous serial communication with built-in
flow control support (UART_CTS, UART_RTS) in the hardware. Parity checking is supported.
UART_TX, UART_RX, UART_RTS, and UART_CTS form a conventional asynchronous serial data port with handshaking. The
interface is designed to operate correctly when connected to other UART devices such as the 16550A. The signaling levels
are CMOS logic levels that track VCC, and are inverted with respect to the signaling on an RS232 cable.
Two-way hardware flow control is implemented by UART_RTS and UART_CTS. UART_RTS is an output and UART_CTS is an
input. Both are active low.
These signals operate according to normal industry convention. UART_RX, UART_TX, UART_CTS, UART_RTS are all CMOS
logic levels that track VCC. For example, when RX and TX are idle they sit at a high logic level (VCC). Conversely for
handshaking pins CTS, RTS at 0 V is treated as an assertion.
The module communicates with the customer application using the following signals (Figure 6):
 Port /TXD of the application sends data to the module’s UART_RX signal line
 Port /RXD of the application receives data from the module’s UART_TX signal line