User's Manual

M2US50NBT/M2SD50NBT
Hardware Integration Guide
Embedded Wireless Solutions Support Center:
http://ews-support.lairdtech.com
www.lairdtech.com/wireless
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Figure 2: Reset Timing
Table 8: Timing Diagram Definitions
Timing
Description
Min
Unit
Tb
Time between VDD33 (3.3V )supplies valid, to SDIO reset (pin-
56;WLAN_PWD_L ) negation.
Note: have suitable 10K ohm Pull-up on SDIO bus, already. No extra
pull-up resistor is required.
5
µsec
Tc
Time between VDD33 (3.3V) supplies valid and
BT_RFKILL (pin-54; BT_PWD_L ) negation
5
msec
Td
Time between SDIO reset (pin-56;WLAN_PWD_L ) negation and
VDD33 (3.3V) invalid, or time between BT_RFKILL (pin-54;
BT_PWD_L ) negation and VDD33(3.3V) invalid.
0
µsec
Tf
Time of SDIO reset (pin-56;WLAN_PWD_L ) assertion during reset
or power down period. 3.3V should keep ON.
5
µsec
Tg
Time of BT_RFKILL (pin-54; BT_PWD_L )assertion during reset or
power down period. 3.3V should keep ON.
5
msec
Important: There is 10K ohm pull high resistor already implemented on SD_D0, SD_D1, and SD_D3. No
external pull-up is required for those three lines.