User's Manual

Table Of Contents

Hardware RESET:

There is on-chip power-on reset circuitry, But can still be used in external reset mode, in this case,

GPIO pin P0.21 as an external hardware reset pin(Active Low). In order to utilize P0.21 as a hardware

reset, the UICR registers PSELRESET[0] and PSELRESET[1] must be set alike, to the value of

0x7FFFFF15. When P0.21 is programmed as RESET, the internal pull-up is automatically enabled.

HW debug and flash programming of Module:

The Module support the two pin Serial Wire Debug (SWD) interface and offers flexible and powerful

mechanism for non-intrusive debugging of program code. Breakpoints, single stepping, and

instruction trace capture of code execution flow are part of this support.

Pin Flash Program interface

SWDIO Debug and flash programming I/O

SWCLK Debug and flash programming I/O

This is the hardware debug and flash programming of module, J-Link Lite support, please refer